Hardware Security Expert
hace 20 horas
Barcelona
We are looking for a Hardware Security Architect with deep RTL and SoC security expertise to join our hardware security team during a period of strong growth. Working closely with the security & certification team, you will own the architecture and design of our hardware Root of Trust, define SoC security requirements spanning secure boot, cryptographic IP, key storage, and lead the triage and mitigation of hardware vulnerabilities across both pre-silicon and fielded products. This is a hands‑on role for someone who enjoys translating high‑level security requirements into concrete RTL‑level architectures, stays current with the latest developments in silicon security and trust architectures, and is comfortable operating both independently and as part of a diverse, collaborative team in a fast‑paced environment. • Strategy & Leadership: Define and lead the hardware security strategy and roadmap for the team in collaboration with the security & certification team, • Architecture Design: Own the hardware Root of Trust (RoT) design and architecture and define SoC hardware security architecture and requirements, covering secure boot, cryptographic IP integration, secure key storage and provisioning, • Lifecycle Vulnerability Management: Lead the triage, analysis and mitigation of hardware weaknesses and vulnerabilities in both pre-silicon and fielded products, • Innovation: Stay at the forefront of hardware security across silicon security, privilege boundaries and trust architectures, • Compliance & Standards: Oversee hardware product compliance with public and private regulations, • RTL & Microarchitecture Implementation: Translate high‑level security requirements into concrete RTL‑level hardware architectures, countermeasures, and microarchitectural mitigations, • Work at one of Europe’s most promising deep‑tech semiconductor scale‑ups, • Accelerated development path, • 4 days per week in the Barcelona office (city center), 1 WFH, • 1 week of work from everywhere in the world, • Competitive package, • A collaborative, technical, and growth‑oriented environment that values direct ownership and clear thinking Must‑Have • Education: Master’s or PhD in Electrical/Electronic Engineering, Computer Engineering, Computer Science, Microelectronics or a related field, • Hardware Design Experience: Minimum of 5 years’ industry experience in the design, microarchitecture and development of SoCs or processors, • RTL Ownership: Deep hands‑on proficiency in SystemVerilog or Verilog, with a proven track record of full‑lifecycle ownership (design, verification, and implementation) of multiple complex blocks, • SoC Security Architectures: Deep understanding of modern SoC security models, including Secure Elements, hardware Root of Trust (RoT), secure boot, and hardware‑software security boundaries, • RISC‑V Architecture: Knowledge of the RISC‑V privileged architecture and its security‑related extensions, • Offensive Security & Hardware Attacks: Practical experience in hardware vulnerability research or low‑level systems security, with strong understanding of hardware debug interfaces and physical/microarchitectural attack vectors, • Low‑Level Software: Experience with low‑level programming languages (C) and working knowledge of assembly language, • Ability to write clear, well‑structured technical reports and document security findings, • Ability to work both independently and collaboratively within a diverse, inclusive team Highly Desirable • Knowledge of open‑source hardware implementations such as Caliptra or OpenTitan, • Familiarity with hardware security analysis techniques such as fault injection and side‑channel analysis, • Understanding of classical and Post‑Quantum Cryptography (PQC) standards, with practical experience implementing them alongside state‑of‑the‑art hardware defenses (e.g., side‑channel attack and fault‑injection countermeasures), • Notion of computer arithmetic and linear algebra as applied to the implementation of cryptographic primitives and hardware accelerators, • Exposure to silicon bring‑up environments or hardware validation workflows, • Familiarity with cloud and datacenter architectures used in AI/ML deployments, • Familiarity with concepts such as confidential computing, virtual machines, remote attestation and trusted execution environments #J-18808-Ljbffr
Marc R.Activo hace 9 minutos
