Sr. Physical Design Engineer
hace 20 días
Farnborough
Experience with COT/ASIC physical design flow covering: Synthesis, Floor‑planning, Place and Route (P&R), Clock Tree Synthesis (CTS), Parasitic Extraction, Static Timing Analysis (STA) and Timing Closure, Physical Verification, Power Analysis, Formal Verification, DFT/DFM and ATPG insertion/patter