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pAlén Space in Nigrán, Spain is expanding its team and seeking a talented DSP Engineer to join their multidisciplinary team of software, FPGA, and digital signal processing engineers. /ppThe ideal candidate will have a Bachelor’s or Master’s in Telecommunications Engineering and over 3 years of experience in designing digital communication systems, particularly with expertise in FPGA implementations and algorithm development. /ppOffering flexible work arrangements, competitive compensation, and a commitment to inclusion and diversity, Alén Space proudly supports professional growth and wellbeing. /p #J-18808-Ljbffr

ph3Overview /h3 pWe´re expanding our team at Alén Space, and are looking for a DSP Engineer; with passion in what you do, talented and experienced. You will be part of a multidisciplinary team of software, FPGA, and digital signal processing engineers and will support the implementation of DSP (Digital Signal Processing) algorithms in programmable devices (FPGAs). /p h3Responsibilities /h3 ul liDesign digital communication systems using platforms including software defined radios (SDRs) and FPGAs. /li liFunctional modeling of DSP algorithms and their implementation in RTL (Verilog/VHDL) or high‑level languages (C/C++). /li liSupport the evolution of our custom space‑tailored radio platforms. /li /ul h3Technical Skills /h3 ul liVerilog / SystemVerilog /li liYosys / Xilinx Vivado /li liPython /li liC/C++ /li liGnuradio /li /ul h3Existing Applications /h3 ul liDVB‑S2 transmitter in Verilog. /li liADS‑B receiver in Verilog. /li liAIS receiver, hybrid between FPGA (VHF channelizer) and CPU (GNURadio/C++). /li liProprietary M2M modem implemented in C. /li /ul h3Qualifications /h3 ul liBachelor or Master’s degree in Telecommunications Engineering. /li liMore than 3 years of experience in developing signal processing algorithms for communication systems in Python, C/C++ or Matlab using both floating point and fixed‑point design techniques. /li liExperience in migrating modeled algorithms to implementations in FPGAs or SDR frameworks. /li liUnderstanding of RF concepts such as AGC, noise figure, power amplifiers, phase noise, PLL, oscillators/mixers. /li /ul h3Valuable Knowledge /h3 ul liExpertise with Software‑Defined Radios (SDR) frameworks such as GNU Radio. /li liExperience with Xilinx Zynq or Xilinx Zynq UltraScale+ series FPGAs, Analog Devices AD9361, and other common RF chipsets. /li liSome experience with Python or other scripting languages. /li liKnowledge of coding theory and techniques: LDPC, Turbo codes. /li /ul h3Benefits /h3 ul liWork remotely a percentage of the time as defined with the manager. /li liFlexible start/finish times; reduced intensive working hours on Fridays and in summer Monday to Friday. /li liCompetitive compensation with ongoing reviews, flexible compensation. /li liWellbeing program: Health, dental, and accident insurance; free fruit and free lunch every Friday and much more. /li liPersonalized career plan development, training, and language learning support. /li liVery committed to inclusion and diversity; we promote equal opportunities in recruitment. /li /ul /p #J-18808-Ljbffr

Necesitaría un reportaje fotográfico de una cafeteríaul br/li¿Qué servicio estás buscando? /li Cafeteria br/li¿Cuántas personas serán fotografiadas? /li Solo local br/li¿Dónde se realizarán las fotos? /li Interior br/li¿Cuántas fotos editadas quieres tener? /li 1 - 10 fotos br/li¿En qué formato necesitas las imágenes? /li Digital o para descargar en línea br/li¿Quieres hacer grabación de vídeo? /li No, no lo necesito br/li¿En qué fecha necesitas al fotógrafo? /li , br/li¿A qué hora? /li 2 horas a las 15:00 pm /ul br/bPreferencia para el servicio: /b Relación calidad/precio

ppJoin our team and build the future of space technology. We're expanding our team at Alén Space, and are looking for a FPGA Engineer with passion in what you do, talented and experienced. You will be part of a multidisciplinary team of software, FPGA, and digital signal processing engineers, contributing to the design, implementation, verification, and validation of FPGA systems for space applications. /p h3What you will be doing? /h3 ul liAnalysis of the FPGA requirements to elaborate the design architecture. /li liDefinition, implementation, verification and validation of designs in RTL (VHDL). /li liElaborate test plans according to the Technical Specification or High-level requirements. /li liWrite test cases in VHDL, Python or C/C++ and execute them during the Test Campaign. /li liWrite documentation across the development cycle (Architecture, Test Plan, Test Report, Manual, etc.). /li /ul h3What Do We Need In Our Team /h3 ul liDegree in engineering: Telecommunications, Electrical, Computer Science, Computer Engineering or similar engineering field. /li liAt least 3 years of experience in FPGA designs. /li liGood understanding of the FPGA architecture, VHDL and Linux. /li liExperience with Xilinx Vivado. /li liExperience with VHDL simulators (Vivado Simulator, QuestaSim or similar). /li /ul pValuable knowledge: /p ul liKnowledge of Xilinx Zynq, MPSoC. /li liExperience with FPGA tools: HDL Designer, Ease HDL, Sigasi, GHDL, Cocotb, etc. /li /ul h3Candidate qualifications and skills /h3 ul liWork remotely a percentage of the time to be defined with the manager. /li liFlexible start/finish times; reduced intensive working hours on Fridays and in summer Monday to Friday. /li liCompetitive compensation with ongoing reviews, flexible compensation. /li liWellbeing program: Health, dental, and accident insurance; free fruit and free lunch every Friday and much more! /li liPersonalized career plan development, training, and language learning support. /li liVery committed to inclusion and diversity; we promote equal opportunities in recruitment. /li /ul pIf you like what you read, then we might have a match. This is the culture we want to have and keep building. So, if that’s also your case, let’s get to know each other! /p h3Ready to take on the challenge? /h3 /p #J-18808-Ljbffr

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