Field-Programmable Gate Arrays Engineer
7 days ago
Oxford
Role: R&D FPGA VHDL Digital Design Engineer Location: Witney, oxford Job Type: Permanent, Full-time – 37.5 hours per week Hybrid: 2-3 days remote work a week depending on design schedule and working on physical products Salary: £60,000 - £80,000 You MUST have experience in CAN and STM32....