Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
11 hours ago
Totowa
Experience planning, architecting, developing, and using constrained random, self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL. Bae is looking for experienced senior level Fpga Design Verification Engineers who can plan, architect, and develop verification environments. Plan, archi...