Mixed-Signal Design & Verification Engineer Lead
3 days ago
Barcelona
ph3Job Summary /h3 pA Mixed-Signal Design Verification Lead will lead, train and mentor the MPS Mixed-Signal Design team and will define and lead the development of the Mixed-Signal Design/Verification framework and infrastructure of complex digital and mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools. Products to be designed/verified may include power management, signal management and mixed signal functions on devices such as switching regulators, sensors, motor control, display drivers, audio amplifiers and power management ICs for a variety of portable and non-portable markets including notebooks, cell phones, telecom, digital cameras, automobiles and network equipment. /p h3Essential Functions /h3 ul liLead, supervise, mentor and train the MPS Mixed-Signal Design Team. /li liSupervise multiple projects to meet quality metrics, deliverables and schedules. /li liParticipate in the Mixed-Signal Design recruitment process. /li liPerform Analog and Mixed-Signal Design, Verification and Validation for projects. /li liDefine and document Analog-Digital Interfaces. /li liModel Analog Blocks behaviorally and analyze architectural choices and trade‑offs. /li liDefine, develop, integrate and verify Analog and Mixed-Signal IP. /li liConduct Analog and/or Digital Mixed-Signal simulations and debugging. /li liAssist the Digital Design Team with Timing, I/O and DFT Constraints. /li liSupport Post‑Silicon Validation and Characterization. /li liMaintain close interaction and collaboration with Analog Design, Analog Layout, Digital Design Engineers, Digital Verification, and Digital Physical Engineers. /li /ul h3Qualifications /h3 ul liBSEE + 12 years of experience; MSEE + 8 years of experience in ASIC Mixed‑Signal design. /li liAbility to work independently and collaborate across teams and departments. /li liStrong leadership skills to manage multiple projects and a small group of Mixed‑Signal Designers. /li liSolid knowledge of the full ASIC development and silicon fabrication process. /li liStrong background in transistor‑level and analog/mixed‑signal circuit design. /li liUnderstanding of device mismatches, noise, linearity and other analog effects. /li liKnowledge of layout design and best‑practice techniques. /li liExperience with simulation tools such as Spectre, HSPICE, or equivalents. /li liProficiency with Cadence circuit design tools like ADE‑L and ADE‑XL. /li liExperience running complex simulations such as Monte‑Carlo, noise simulations, and stability analysis. /li liExperience running DRC and LVS using Calibre, ICV, etc. /li liExperience with Verilog‑AMS mixed-mode simulations and Verilog, System Verilog and Verilog‑A coding for behavioral modeling. /li liKnowledge of DFT Techniques such as SCAN, LBIST, ABIST and IDDQ. /li liKnowledge of STA and Mixed‑Signal Timing and I/O Constraints for Syn and PR. /li liExcellent written and verbal communication skills and strong teamwork and collaboration. /li liKnowledge/Experience with Automotive and ASIL Standards is a plus. /li /ul h3Additional Knowledge /h3 ul liPower management industry/applications. /li liProtocols: I2C, I3C, SPI, USB, PMBUS. /li liExperience with GitLab and Cliosoft SOS. /li /ul h3Location /h3 pBarcelona, Spain or Portugal /p h3EEO Statement /h3 pMonolithic Power Systems, Inc. (MPS) is an Equal Opportunity Employer and embraces diversity in our employee population. It is the policy of MPS to provide equal opportunity to all qualified applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, protected veteran status or special disabled veteran, marital status, pregnancy, genetic information, or any other legally protected status. A valid disability certificate will be considered a plus as part of our commitment to workplace inclusion and diversity. /p /p #J-18808-Ljbffr