Server CPU Physical Design Engineer, Senior/Staff level - Cambridge, UK
hace 4 días
Cambridge
\n Job Overview\n Qualcomm Technologies International Ltd is seeking talented Physical Design Engineers to join the Nuvia CPU team in Cambridge, UK. The team develops next‑generation, high‑performance, power‑efficient custom CPU cores for advanced compute and server‑class platforms. The role ranges from Senior Engineer to Staff Engineer, with responsibilities, ownership, and technical leadership scaling with experience. Key Responsibilities\n \n • Own or contribute to CPU block implementation from RTL/netlist to GDS, including synthesis, floorplanning, power planning, placement, clock tree synthesis, routing, optimization, ECOs, and sign‑off.\n, • Drive timing closure and physical implementation convergence across multiple modes, corners, and operating conditions.\n, • Work on high‑performance, low‑power CPU designs with demanding performance, power, and area targets.\n, • Debug and resolve complex implementation issues related to timing, congestion, clocking, routing, IR drop, power integrity, EM, ECO closure, DRC/LVS, and physical verification.\n, • Collaborate closely with RTL, architecture, circuits, CAD, SoC, and post‑silicon teams to improve design quality, implementation efficiency, and product performance.\n, • Evaluate and contribute to the design process from concept through productization, including architecture definition, feasibility analysis, pre‑silicon design and verification, and post‑silicon validation.\n, • Develop and enhance physical design flows, automation, and methodologies to improve productivity and quality of results.\n, • Use data‑driven analysis to identify implementation bottlenecks, improve design convergence, and push PPA beyond standard targets.\n, • For Staff‑level candidates, provide technical leadership, mentor engineers, define implementation strategies, and drive closure of critical CPU blocks or methodology initiatives.\n Required Skills and Experience\n \n, • Strong experience in physical design implementation, including synthesis, floorplanning, placement, CTS, routing, timing closure, ECOs, and sign‑off.\n, • Strong understanding of static timing analysis and timing closure methodologies, and trade‑offs between timing, power, area, congestion, and routability.\n, • Knowledge of high‑performance and low‑power implementation techniques.\n, • Hands‑on experience with industry‑standard EDA tools for synthesis, place and route, STA, power analysis, physical verification, and sign‑off (e.g., Genus, Innovus, Fusion Compiler, PrimeTime, Tempus, Voltus, RedHawk, Conformal).\n, • Ability to debug complex physical design issues across timing, congestion, clocking, routing, power, and verification domains.\n, • Scripting and automation experience using TCL, Python, or Perl.\n, • Strong communication skills and the ability to work effectively in a global, cross‑functional engineering environment.\n Minimum Qualifications\n \n, • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant experience in ASIC, CPU, or physical design implementation.\n, • Master’s degree with relevant hardware engineering experience, or a PhD with relevant CPU/ASIC/physical implementation experience.\n Preferred Qualifications\n \n, • Physical design experience on CPU cores, high‑performance compute blocks, or timing‑critical ASIC designs.\n, • Experience working in advanced semiconductor process nodes, especially 7nm and below.\n, • Strong understanding of CPU PPA optimization and design convergence.\n, • Experience with low‑power design techniques, clock optimization, useful skew, standard‑cell library usage, and physical‑aware optimization.\n, • Knowledge of power integrity, IR drop, EM analysis, and power sign‑off.\n, • Experience with timing ECOs and late‑stage design closure across large scenario sets.\n, • Understanding of CPU microarchitecture, logic design, or circuit‑level implementation considerations.\n, • Experience developing physical design methodology, automation, or productivity‑enhancing flows.\n, • For Staff‑level candidates, proven ability to lead complex technical work, influence cross‑functional teams, and mentor other engineers.\n What We Value\n \n, • Strong physical design fundamentals and enthusiasm for solving difficult implementation problems.\n, • Passion for pushing performance, power, and area to best‑in‑class levels.\n, • Ability to work independently while collaborating effectively across global teams.\n, • Structured, analytical approach to debugging, optimization, and design closure.\n, • Motivation to build high‑performance, power‑efficient server CPU products.\n, • Demonstrated ownership, technical curiosity, and a continuous‑improvement mindset.\n Benefits and Perks\n \n, • Competitive compensation package, including base salary, performance‑related bonus, and equity opportunities.\n, • Employee Stock Purchase Plan and equity programs.\n, • Pension and retirement support, including a matching pension scheme.\n, • Health and wellbeing benefits, including medical, life, income protection, and wellbeing resources.\n, • Maternity, paternity, family, and extended leave support.\n, • Education assistance and tuition support.\n, • Relocation and immigration support where applicable.\n, • Employee assistance and resilience programs.\n, • Opportunities to connect through employee networks, community programs, volunteering, and social groups that support inclusion and collaboration.\n, • Subsidised wellbeing and lifestyle benefits, such as gym or fitness support and bicycle purchase schemes.\n, • A flexible, collaborative, and technically challenging work environment.\n \n Qualcomm is an equal opportunity employer. If you are an individual with a disability and need accommodation during the application/hiring process, please contact Qualcomm’s accessibility team at disability‑accommodations@qualcomm.com. Qualcomm is committed to providing reasonable accommodations. \n For more information about this role, please contact Qualcomm Careers. \n #J-18808-Ljbffr
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