Technical Manager, Physical Design (ASIC/SoC Place & Route) (San Jose, CA)(5572)
3 days ago
San Jose
Overview of Role
As a Physical Design Engineer, you will be responsible for the entire APR implementation flow from RTL-to-GDS that includes floorplan, place and route, CTS, STA, PDV/EMIR/Noise/SigEM cleanup and signoff on lower power SoC blocks. You will be reporting to Manager of Advanced Chip ...