Dsp jobs in San Jose, California - Page 2Create job alerts

The role involves modeling and simulation of DSP algorithms, verification of hardware implementation, and collaborating on software development.

Front-End ASIC Design Engineer - Milpitas, CA Unique opportunity to join an established international company in their US expansion. Working from the US headquarters, you will have the ability to be an impact player working with other exceptionally talented people. The Front-End ASIC Design Engineer will be a key person in this growing design department. Micro-architecture experience is required. Great opportunity to work on current, ongoing and upcoming new projects. Hybrid remote/onsite position. Primary responsibilities include: Support customer’s design through all phases of ASIC execution. Ensure designs meets product performance requirements by performing related tasks. Contribute to microarchitecture, RTL design, synthesis, and timing closure. Ensure deadline for project milestones are met. Work effectively with internal teams, including verification, FPGA, Firmware and physical design teams, some globally. Display a results-focused attitude and accomplish Company/Team-goals. Required/Desired Qualifications: Bachelor’s Degree in EE or similar degree, MS preferred 3-8++ years of professional design experience Front-end ASIC design and Micro-architecture experience are keys. SoC experience is greatly preferred, but candidates having strong, recent front-end ASIC design will be considered. SOC design experience - integrate IP’s into SoC’s for customers Hands-on ASIC front-end design, ideally in design services environments (product backgrounds acceptable) Experience interfacing with customers and full-lifecycle of major projects in a small environment is required Skills Required / Preferred – Micro-architecture at module/sub-system/chip-level; digital design of complex modules/sub-systems, with solid understanding of clock-domain crossings; integration of IPs/modules/sub-systems designed by internal/external teams; experience using AMBA bus protocols; System Verilog experience; Lint and CDC analysis; timing analysis; excellent debug skills; customer support Teamwork, dedication, collaborative, strong communications and interpersonal skills Ability to meet stringent deadlines and project timelines Skills Desired - Experience in at least few of these: CPU (preferably, ARM), or GPU, or DSP; low-power design and verification; peripheral interfaces such as CSI, I3C, USB, PCIe; FPGA; image/video processing

Compensation: Starting $25 per hour + Bonus.Shift Time: Monday to Sunday 10:00AM to 10:00PM (Based on Peak/Prime Season).Competitive wages, PTO and Seasonal Bonuses.Be part of a local business that is making a positive impact on the community.As a Delivery Driver at TOLT, you will play a crucial rol

Job DescriptionSalary: $110,000 to $200,000 DSP System Architect We are seeking a DSP System Architect to optimize digital signal processing (DSP) architectures for high-speed SerDes (Serializer/Deserializer) transceivers. This role defines system-level architecture, algorithms, and performance needs. The architect will work closely with cross-functional teams to debug, analyze data and bring SerDes solutions to market. Key Responsibilities • Collaborate with analog, digital, and mixed-signal design teams to implement DSP solutions., • Collaborate with application and firmware team participate in silicon bring-up and debugging by analyzing data and provide guidance on test plans for lab characterization and verification, • Assist customers on system-level performance and algorithmic issues., • Define and design DSP architectures for high-speed SerDes and optical transceivers., • Develop and maintain end-to-end system models using tools like MATLAB, Simulink, C, and/or Python., • Design and simulate DSP algorithms for signal processing in high-speed links, including equalization, timing recovery, and error correction (FEC)., • Perform research and development activities to advance DSP for SerDes and optical channels., • Develop and perform behavioral modeling of mixed-signal circuit designs for transceivers. Basic Qualifications • Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field., • 0-7+ years of experience in DSP system architecture and algorithm development for high-speed SerDes or communication systems., • Understanding of digital communication and signal processing theory, including:, • Channel equalization techniques (e.g., FFE, DFE), • Timing recovery and CDR (Clock and Data Recovery) architectures, • Detection and estimation theory, • Adaptive algorithms and system identification, • Proficiency in communication system modeling using tools like MATLAB, Simulink, C, and/or Python., • Experience with high-speed serial data protocols (e.g., NRZ, PAM4) and relevant industry standards., • Familiarity with mixed-signal circuit design concepts and their impact on DSP performance., • Experience in guiding and testing the transfer of algorithms from high-level models to RTL implementation., • Communication, problem-solving, and collaboration skills. Preferred Skills: • Experience with advanced modulation formats (e.g., PAM4)., • Experience with ADC-based wireline transceivers and/or coherent DSP architectures., • Familiarity with FEC (Forward Error Correction) techniques, such as RS or LDPC codes., • Familiarity with lab equipment for testing high-speed serial links (e.g., oscilloscopes, spectrum analyzers)., • Experience with machine learning concepts and their application in DSP., • Knowledge of analog mixed-signal circuit design concepts., • Experience in firmware or embedded software development.