Senior IP Design Engineer
11 days ago
Bexleyheath
We are seeking a Senior IP Design Engineer to support advanced development work on high-performance FPGA and Adaptive SoC platforms. This is a 6-month contract working with cutting-edge technology across high-speed networking, RTL design, and complex SoC architectures. The role involves designing and delivering SystemVerilog RTL IP, integrating high-speed interfaces, and driving improvements across synthesis, place & route, timing closure, and automation flows. You will work closely with architecture, RTL, verification and integration teams to deliver optimised IP targeting modern Adaptive SoC devices. Key Responsibilities * Develop and implement SystemVerilog RTL for FPGA / Adaptive SoC designs * Design and optimise high-speed connectivity IP (PCIe Gen5, 100Gb Ethernet, AXI/AMBA) * Support synthesis, P&R, timing analysis and timing closure * Collaborate with cross-functional teams on integration and validation * Contribute to CI/CD workflows, scripting, and automation (Python, Tcl) * Provide documentation, status updates and technical input Required Skills * Strong SystemVerilog RTL design background for FPGA / SoC * Hands-on experience with AMD/Xilinx toolchain – Vivado, Vitis * Expertise in PCIe, 100GbE, AXI/AMBA, and high-speed interface design * Experience in synthesis, place & route, timing closure * Scripting in Python and Tcl; experience with Git and CI pipelines Ideal ...