Principal ASIC Design Engineer - RTL, PCIe, CXL
2 days ago
San Jose
Job Title: Principal ASIC Design Engineer - RTL, PCIe, CXL Job Location: San Jose, CA Compensation: $180K - $240K base Depending on experience plus stock options! Requirements: RTL Design, ASIC Design, Microarchitecture, PCIe, CXL We were founded in 2020 by a team of veterans in Silicon Valle...