Trabajos cadence en San Jose, California - Page 4Crear alertas

Job DescriptionReady to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life. The Senior PCB Layout Engineer is responsible for leading the physical implementation of complex, high-performance printed circuit boards from concept through production. This role requires deep expertise in multi-layer, high-speed, RF, and mixed-signal PCB layout, strong ownership of stackup and via architecture decisions, and direct engagement with PCB fabrication and assembly partners to ensure manufacturability, reliability, and cost efficiency.What you will do • Technical Leadership· Lead PCB layout architecture for complex multi-layer designs (10–20+ layers) including high-speed digital, RF, analog, and power circuitry· Define and own stackups, impedance models, and via strategies (through, blind, buried, microvias, backdrilling)· Serve as the DFM authority for layout decisions, balancing electrical performance, cost, yield, and reliabilityAdvanced PCB Design & Layout· Perform and guide component placement optimizing signal integrity, power integrity , EMI/EMC, thermal, and mechanical performance· Route high-speed serial interfaces, differential pairs, controlled-impedance nets, and sensitive RF/analog signals· Design robust power distribution networks and grounding structures· Apply advanced shielding and isolation techniques for EMI/EMC controlFabrication & Assembly Interface· Lead DFM/DFA reviews with PCB fabrication and assembly partners· Resolve complex DFM issues related to:o HDI structures and sequential laminationo Via consolidation, backdrilling, and drill count reductiono Stackup optimization for yield and cost· Optimize designs for manufacturability, reliability, and volume productionCross-Functional Collaboration· Work closely with electrical, mechanical, test, and manufacturing engineers throughout the product lifecycle· Support board bring-up, debug, ECOs, and production transitions· Mentor and technically guide junior PCB layout engineersDocumentation & Process Ownership· Create and review stackup drawings, fabrication notes, assembly notes, and manufacturing data packages (Gerber / ODB++)· Establish, maintain, and enforce PCB layout standards and best practices· Drive continuous improvement in layout quality, DFM compliance, and cost efficiency What you bring to this role, • 7+ years of hands-on PCB layout experience delivering complex designs from concept to production, • Expert-level proficiency in PCB layout tools such as Altium Designer, Cadence Allegro, • PCB stack-up development for digital, power, and RF designs, • Impedance-controlled routing and transmission-line design, • Power-distribution layout, plane design, and current-density management, • Mixed-signal layout techniques (digital, analog, RF isolation and partitioning), • Component placement strategy for manufacturability, signal integrity, and thermal performance, • Design-rule and constraint creation (clearances, lengths, impedance, vias, creepage/clearance), • Layout documentation (fab drawings, assembly drawings, layer stack tables, notes), • Footprint library creation and maintenance; Altium librarian responsibilities, • Understanding of high-speed signal attenuation, dispersion, and copper-loss mechanisms, • Crosstalk awareness and mitigation through routing and spacing techniques, • RF parasitic effects (stray C/L/R) and reduction methods in layout, • RF isolation techniques (ground fencing, stitching vias, partitioning, shielding)Bonus points for the following, • Bachelor’s degree in electrical engineering, Computer Engineering, or a related field (Master’s degree is a plus)., • Familiarity with advanced PCB fabrication technologies such as mSAP (Modified Semi-Additive Process) and SLP (Substrate-Like PCB), including fine-line routing, small via structures, and associated DFM constraints • An opportunity to really make a difference• Sustainability at our core• Fair and honest workplace• Innovative thinking is encouraged• Competitive salaries• Continuous learning and development• Health and wellness care options• Financial solutions for the future • Optional legal services (US only)• Paid holidays• Paid time off

Job Description About the Role We are seeking a highly skilled Silicon Photonic IC Design Engineer to play a key role in the design and physical layout of advanced Silicon Photonic Integrated Circuits (PICs) that interface directly with custom ASICs built on leading-edge semiconductor process nodes. This position offers the opportunity to work at the intersection of photonics, analog, and digital design — helping to define and deliver next-generation optical and electronic systems. Key Responsibilities * Contribute to the design and physical layout of complex Silicon Photonic ICs (PICs) that connect directly with advanced ASICs. * Participate in all stages of PIC delivery — from floor planning and block placement to micro-architecture, optical/electrical routing, and back-end verification (DRC/LVS). * Collaborate with analog, digital, and packaging teams to ensure optimal design outcomes that meet requirements for opto-electronic performance, signal integrity (SI), and power integrity (PI). * Work closely with other photonics engineers to refine layout methodologies, improve design automation, and enhance existing software-based verification and layout flows. Qualifications Specialized Skills * Strong understanding of photonics fundamentals and core engineering design principles. * Hands-on experience with Silicon Photonics Process Design Kits (PDKs) and best practices for designing and laying out photonic components, subsystems, and complete PICs. * Proficiency with physical design tools such as Cadence, Siemens Mentor, or Klayout, including scripting and automation using SKILL or Python. * Familiarity with layout verification tools (e.g., Calibre, Pegasus) for DRC, ERC, and LVS checks. * Experience with SI and PI-aware electrical routing for mixed-signal and digital designs is a strong advantage. Education * Ph.D. in Electrical Engineering, Physics, or a related field with a focus on integrated photonics or optical device design. Preferred Attributes * Highly self-motivated with a proactive approach to problem-solving. * Creative thinker with strong attention to detail. * Thrives in a collaborative and fast-paced environment. * Excellent written and verbal communication skills. California Pay Range$185,000—$225,000 USD

Job Description Come join VisitorsCoverage, one of Silicon Valley's most successful InsurTech companies, certified as a Great Place to Work! We are looking for a Insurance Partner Operations Lead to join our growing team. This person will design and run a scalable way to onboard, manage, support, and communicate with external partners (such as agents, brokers and insurance carriers). This role owns the full partner lifecyclecreating clear workflows, routines, escalation paths, and feedback loops that speed things up and reduce reliance on individual people. Youll work closely with internal teams (Operations, Support, Sales/Marketing, Product, and Implementation) and external partners to ensure insurance carrier launches, product and plan updates, and agent onboarding run smoothlywithout needing executive involvement for everyday decisions. We are located in Santa Clara, California, and are looking for local candidates only. Must be willing to commute to the Santa Clara office 4 times a week. Candidates with authorization to work in the US preferred. No new H1B visas will be processed, but a H1B transfer may be considered for the right candidate. What We Do: VisitorsCoverage is an Insurtech company, located in the heart of Silicon Valley, revolutionizing the way travelers search, compare, purchase, and manage their travel insurance. Imagine a place where buying travel insurance is as easy as ordering an item from your favorite online retailer. You know exactly what the benefits are and what each word on the coverage document means, and you are able to zip through the checkout process. We are obsessed with simplifying Travel Insurance! We wake up everyday thinking of new ways to meet the same expectations that users have from their online retailers and delivery or streaming services. We are a team of people who counter the thought that insurance is boring and love the challenge of delighting our users at every step of their decision-making process. If this sounds like the perfect role and workplace for you, we encourage you to apply for this position! VisitorsCoverage is on a mission to hire only the best, and we are committed to providing exceptional employee experiences with meaningful work and true work/life balance. Requirements Key Responsibilities: • Manage partner and provider relationships., • Be the key point of contact between insurance carriers, internal stakeholders and agents for information exchange., • Effectively manage provider onboarding, plan changes and keep all parties in sync., • Build standardized intake processes for plan changes/go-lives, ensure documentation completeness, and eliminate handoff ambiguity., • Create comms playbooks and templates, maintain distribution lists, and log announcements for auditability., • Define KPIs, build dashboards, review trends, and drive corrective actions., • Train internal teams and partners on the new workflows; reduce dependency on tribal knowledge., • Ability to communicate clearly and confidently across email, meetings, and in-person settings, and to produce high-quality playbooks, guides, and partner-facing documentation., • Summarizing risks, tradeoffs, and decisions when escalation is needed., • Excellent stakeholder management with the ability to influence without authority (internally and externally)., • Ownership mindset comfortable owning ambiguous, end-to-end problem spaces., • Bias for action pragmatic, execution-focused, and comfortable iterating., • Customer/partner empathy designing processes that work in the real world., • Bachelors degree or equivalent experience within a related field., • 4-6 years of experience in partner operations, business operations, implementation operations, or similar cross-functional ops roles, including managing external partner., • Demonstrated ability to build a standardized operating cadence and drive adoption across multiple teams and partner types., • Experience within insurance-related environments or fields is strongly preferred., • Experience working in a fast-paced, tech-driven professional environment is a plus., • 100% company paid individual medical, dental, & vision insurance coverage, • Pet insurance, • Paid parental leave, • 401(k) retirement plan, • Paid time off for annual charity or volunteer work, • Generous paid time off, • Fitness/Wellness gym stipend

Job Description Title : School Outreach Coordinator Location: Silicon Valley (Cupertino / Los Altos / Stevens Creek and nearby areas) Schedule: Tuesday–Saturday Pay: $22–$30/hour Type: Part-time / Full-time (based on availability) About Think Academy Silicon Valley Think Academy is a leading math enrichment program serving Silicon Valley families with rigorous, joyful learning experiences. We partner with local schools and communities to support students' academic growth and confidence. Role Summary We're looking for an Outreach & Partnerships BD who thrives in the community—building relationships with schools, PTAs, preschools, and local organizations and turning partnerships into real enrollment outcomes. This role owns the "front door" of local growth: outreach strategy, school relationship development, on-site events, and building a small field outreach team. Key Responsibilities1) School & PTA Partnerships (Core) • Build and manage relationships with elementary schools, middle schools, PTAs, and school district communities, • Identify partnership opportunities (e.g., Math Night, STEM Night, silent auctions, newsletters, after-school enrichment, PTA sponsorships), • Pitch collaboration proposals and coordinate logistics, approvals, and follow-up, • Maintain a partnership pipeline and report weekly progress (contacts made, meetings booked, partnerships secured) 2) Preschool & Early Childhood Outreach, • Develop partnerships with preschools, daycare centers, and early childhood programs, • Coordinate co-marketing opportunities (parent workshops, flyers, referral programs, classroom visits where allowed), • Build a repeatable playbook for preschool outreach in key neighborhoods 3) Field Outreach Team Building ("Ground Team"), • Recruit, train, and manage a small team of outreach reps/volunteers (students, parents, part-time reps), • Create field scripts, daily task lists, and quality standards, • Strong communication skills; comfortable reaching out cold and following up, • Highly organized; able to manage multiple relationships and event logistics, • Experience working with schools, PTAs, preschools, or youth/community organizations, • Bilingual English/Chinese is a plus (not required), • Familiarity with Silicon Valley school communities or local parent networks, • Experience training/managing a small field team

Job DescriptionnEye.ai, a well-funded optical switch startup, is poised to revolutionize the future of data centers. nEye’s MEMS-based silicon photonics optical circuit switches (OCS) eliminate critical bottlenecks in AI processing by enabling direct optical connections among thousands of GPUs and memory units. The company's SuperSwitch is an ultra-low power consumption, high radix, compact chip-scale design, offering hyperscale data centers enhanced performance, efficiency, and scalability. Job Overview We are seeking a highly technical MEMS Integration Engineer to bridge the gap between our internal design engineering teams and external foundry partners. This role requires a strong foundry process engineering background combined with the strategic oversight of a foundry manager. You will be responsible for owning the technical execution of product development, driving new product introduction (NPI), and ensuring the successful transfer of our Silicon Photonics and MEMS processes to high-volume manufacturing. Your success will ensure seamless integration and alignment with nEye's device specifications, optimizing device performance, reducing unit costs, and maximizing wafer yield through continuous improvement.Key Responsibilities • Product Development & Transfer: (1) Partner closely with design engineering and fabs to define, develop, and refine process flows for new MEMS products. (2) Oversee the end-to-end NPI lifecycle, from process transfer to external foundries, ensuring manufacturability and repeatability. (3) Act as the primary technical interface between nEye’s design team and foundry integration engineers., • Foundry Process Engineering: (1) Design, document, and execute end-to-end MEMS process flows. You will integrate diverse modules (lithography, etch, thin films) into a cohesive fabrication sequence. (2) Develop and maintain rigorous process specifications, utilizing deep expertise in diverse fabrication modules including lithography, etch, and deposition to ensure seamless integration. (3) Wafer Bonding Implementation: Act as the Subject Matter Expert (SME) for back-end bonding technologies, including: anodic, fusion, eutectic, and hybrid bonding to achieve long-term hermeticity; Surface preparation and activation (plasma/chemical); Management of Thermal Expansion (CTE) mismatch and bond-induced stress. (4) TSV & 3D Integration: Lead the development and integration of Through-Silicon Vias (TSVs) for advanced device packaging. (5) Manage Foundry Tape-out activities, ensuring successful execution and alignment with project timelines. (6) Own the technical execution of the fabrication schedule, foundry activities and deliverables to ensure on-time wafer out. (7) Monitor Statistical Process Control (SPC) and address Out of Control (OOC) events immediately., • Yield & Failure Analysis: (1) Analyze metrology data (SEM, AFM, C-SAM, IR, profilometry) to identify failure modes in the bond interface (e.g., voids, delamination) and implement corrective actions. (2) Track, analyze, and report on key process and device performance metrics, identifying opportunities for performance uplift and process simplification. (3) Lead Root Cause Analysis (RCA) and 8D reporting for process deviations or hardware failures, working closely with foundry FA labs. (4) Drive Continuous Improvement Plans (CIP) to optimize device performance, reduce unit costs, and maximize wafer yield.Required Experience, • BS, MS, or PhD in Electrical Engineering, Mechanical Engineering, MEMS, Applied Physics, Materials Science, or a related technical field., • 5+ years of hands-on experience in foundry process engineering, MEMS, or CMOS process development and integration., • Product Experience: Proven track record managing tape-outs and taking products through the NPI lifecycle into high-volume manufacturing within a foundry environment., • Process Architecture: Proven track record of architecting and executing successful, end-to-end MEMS process flows. Must demonstrate the ability to balance thermal budgets and material compatibility across complex modules., • Advanced Wafer Bonding: Deep expertise in Wafer-to-Wafer (W2W) integration, including surface activation, alignment tolerances, and various bonding techniques (Fusion, Anodic, Eutectic, or Hybrid)., • Experience with Through-Silicon Via (TSV) integration, Cavity SOI processing, and management of TSV-induced thermo-mechanical stress in bonded wafers., • Proficiency in SPC methodologies, yield analysis software, and a solid understanding of cleanroom practices.Preferred Experience, • Experience leading foundry-facing engineering initiatives., • Layout & DFM: Proficiency in L-Edit, Cadence, or KLayout., • Ability to lead Mask Floorplanning, including the strategic placement of Process Control Monitors (PCMs), alignment marks, and dicing streets., • Mastery of quality control methods, including 6-sigma, 8D, and FMEA.

Job Description We are seeking a modeling Engineer to develop high-level models of complex SoC hardware. The virtual platforms combine models of custom hardware accelerators for vision, 2D and 3D graphics, machine learning and more, within a multi-core, multi-level memory hierarchy SoC architecture, and serve as the primary simulation vehicle for system software and firmware. The ideal candidate will be proficient in hardware simulation using C++, and understand the firmware development processes. Responsibilities • Design and develop SystemC TLM models to accurately represent the SoC architecture integrating emulated processors, DSPs, Network-on-Chip, DMA and memory controllers, etc…, • Integrate first-party and vendor models into the Virtual Platform, develop automated workflows to ensure register-level accuracy and complete connectivity at the SoC level, minimizing manual intervention and enabling continuous integration., • Collaborate with silicon architects, digital designers and verification engineers to design and develop high-fidelity, fast C++ models for first-party IP., • Coordinate virtual platforms with hardware development programs, validating multiple SoCs and architectural changes with system software and firmware engineering, enabling end-to-end silicon validation test frameworks., • B.S. degree in Computer Science or Electrical Engineering or equivalent experience., • 2+ years experience in hardware model simulation, virtual platform, performance modeling of complex SoCs or high-fidelity hardware accelerators., • High proficiency in modern C++ in the domains of chip-design, electronic design automation or simulation., • General familiarity with SoC components: embedded processors such as ARM A/M series, Risc-V, DSP, DMA, Cache Hierarchy, DRAM, Network-on-chip, AMBA protocols. Extensive experience in at least one of these areas., • Experience with modern buildframeworks and continuous integration systems, such as CMake, Bazel and CI frameworks such as Jenkins, GitLab CI/CD., • Experience with debugging and profiling tools, such as GDB or other debuggers Preferred qualifications • Experience with the SystemC/TLM library, • Experience with virtual platform development tools and frameworks, such as Synopsys Virtualizer, Cadence Virtual Platform, Imperas OVP, or ARM Fast Models, • Familiarity with processor/DSP architectures, such as ARM, RISC-V, and XTensa, • Familiarity with NoC, MMU, address translations, and cache modeling, • Familiarity with the standard C++ concurrency support library: threads, atomic operations, memory ordering, etc…, • Proficiency in Python to automate design flows, creation of collateral data, • Experience with high level C/C++ synthesis (HLS), • Working knowledge of Verilog California Pay Range$70—$75 USD

Job Description About Etched Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary Etched is looking for exceptional Physical Design engineers to join our team. In this role, you will own block-level implementation and verification, drive timing closure and PPA optimization, supervise 3rd party design work, and help improve our design flows and iteration speed. Key Responsibilities * Deeply understand what is involved in physical design * Running PD flows to close blocks, support ASIC infrastructure, automate PD flows, improve CAD infrastructure * Collaborate with RTL Designers and provide Physical Design feedback to improve PPA * Drive dashboards that show the convergence of projects related to PD * Optimize tool flows, working with EDA vendors to incorporate the latest features * Accountable for block level closure * Supervise the outsourcing of physical design to a 3rd party service You may be a good fit if you have * 5-10+ years of previous experience with PD * Tools, flow, and design methodology from RTL synthesis to GDSII sign-off * Experience with back-end design and timing closure on advanced process nodes (5nm and below) * Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler) automated RTL-to-GDSII flows * Experience with sign-off tools (PrimeTime, Tempus, Voltus, etc.) * Experience with UPF-based low power design methodology, power verification,synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS, routing, IR drop, and EM/antenna analysis * Deeply creative and able to think from first principles Strong candidates may also have experience with * Familiarity with transformer models and machine learning * Ability to program with Python or another scripting language * Familiarity with AI tools for programming/coding * Startup experience or comfort working in fast-paced environments Benefits * Medical, dental, and vision packages with generous premium coverage * $500 per month credit for waiving medical benefits * Housing subsidy of $2k per month for those living within walking distance of the office * Relocation support for those moving to San Jose (Santana Row) * Various wellness benefits covering fitness, mental health, and more * Daily lunch + dinner in our office How we’re different: Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs. We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed. Compensation Range: $150K - $275K

Job DescriptionCompany Description Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description Job Description: Join our dynamic FPGA (Field Programmable Gate Array) Business Unit as a Technical Staff SOC Architecture Engineer. We are at the forefront of developing SOC FPGA compute platforms for a diverse range of low-power applications, including smart embedded vision, industrial IoT, access/gateways/aggregation networks, and compute platforms for aerospace and defense. As an SOC Architect, you will collaborate with a team of highly motivated architects and senior designers to define and deliver next-generation, power-optimized FPGA solutions. Key Responsibilities: • Lead technical diligence and perform trade-off analysis of product requirements during the Product Concept Phase, translating them into actionable Design Requirements for the Product Definition Phase., • Collaborate with Embedded Software teams to define optimal Hardware Abstraction Layer (HAL) and driver interfaces, ensuring seamless integration and performance., • Develop detailed microarchitectural specifications, ensuring accurate capture of design intent, identifying technical gaps, and proposing effective remedies., • Drive RTL implementation and partner with Logic Verification and ASIC Implementation teams through synthesis and DFT insertion., • Lead discussions with CPU and IP vendors to shape future features and requirements., • Develop and utilize techniques and tools for SOC benchmarking and bandwidth analysis, delivering optimized system solutions., • Work cross-functionally with Functional Verification, ASIC Implementation, and Embedded Software teams across multiple geographical locations., • Oversee all facets of interconnect to FPGA fabric, associated peripherals, and IO resources, extending beyond the SOC boundary.Qualifications Requirements/Qualifications: Minimum Qualifications: • Master’s degree in Electrical Engineering, Computer Science, or equivalent practical experience., • 10–15 years of industry experience in SOC architecture and design., • Proven experience developing ARM M-Class or RISC-V Embedded SOC architectures., • Expertise in SOC advanced interconnect, AMBA, SOC peripherals, and DDR memory., • Proficiency in developing microarchitecture specifications, RTL design, and logic simulations., • Hands-on experience with Verilog, Cadence/Synopsys/Siemens simulation environments, synthesis, and DFT insertion EDA tools., • Strong scripting skills in CSH/BASH, PERL, or Python., • Demonstrated adaptability and flexibility in a fast-paced, evolving environment., • Excellent verbal and written communication skills, with the ability to convey complex technical concepts to cross-functional teams., • Proactive problem-solving attitude and a willingness to take initiative in addressing technical challenges. Preferred Qualifications: • Experience in SOC architecture performance analysis, tools, and simulators at various abstraction levels (Cycle Accurate, TLM, and/or Functional)., • Familiarity with UVM and functional coverage methodology., • Experience with vector processing micro-architectures is a major plus. Additional Information Travel Time: 0% - 25% Physical Attributes: Feeling, Handling, Hearing, Other, Seeing, Supervises Others, Talking, Works Alone, Works Around Others Physical Requirements: 10% walking, 10% standing, 80% sitting; 100% in doors; Usual business hours Pay Range: We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading ESPP program with a 2 year look back feature. Find more information about all our benefits at the link below: Benefits of working at Microchip The annual base salary range for this position, which could be performed in California, is $88,000 - $232,000.* *Range is dependent on numerous factors including job location, skills and experience. Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law.

Job Description Responsibilities: • Develop full-custom Analog/Mixed-Signal/RF layouts at block and top level., • Ensure compliance with Analog/Mixed-Signal and RF design constraints., • Maintain layout quality, including matching, symmetry, shielding, isolation, and reliability per design guidelines., • Perform DRC/LVS/ERC and antenna checks and drive layout closure., • Hands-on experience with:, • Cadence Virtuoso (XL/GXL) for layout design., • Calibre for verification., • PDKs with multi-patterning rules., • Experience in lower technology nodes, preferably 5nm and below., • RF layout experience, including:, • Handling high-frequency signal paths, guard rings, shielding, and EM coupling considerations., • Exposure to PLL, LNA, VGA, ADC, DAC, SerDes, Bandgap, LDO, etc., • B.Tech/B.E/M.Tech/M.E in ECE/EE. Kaleidoscope, an Infosys Company, is an equal opportunity employer, and all qualified applicants will receive consideration without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, spouse of protected veteran, or disability.

Job DescriptionSalary: 180000-190000USD Annual Base Senior Applications Engineer Power Management (DC/DC Buck Converters) Position Summary We are seeking an experienced Senior Applications Engineer with deep, hands-on expertise in DC/DC buck converters and power management ICs. This role requires strong system-level design, validation, and device debug skills. The Senior Applications Engineer will act as a technical leader, supporting complex customer designs, driving root-cause analysis, and collaborating closely with R&D, validation, and marketing teams to ensure robust product adoption and successful customer deployments. Key Responsibilities • Serve as a technical expert for DC/DC buck converter products, supporting customers from initial architecture through production release, • Lead hands-on lab activities including schematic development, PCB bring-up, validation, and device debug of power management ICs, • Design, build, and debug evaluation modules (EVMs) and customer reference designs, • Perform detailed system-level validation including efficiency, transient response, stability, thermal, protection features, and reliability testing, • Drive root-cause analysis of device, system, and layout-related issues using bench measurements and failure analysis techniques, • Review and approve customer schematics and PCB layouts, providing expert guidance on power integrity, grounding, EMI/EMC, and thermal performance, • Partner closely with IC design, validation, and test teams to debug silicon issues and influence product improvements, • Support customer development schedules by providing timely, technically sound recommendations and solutions, • Develop and own high-quality technical collateral, including:, • EVM Users Guides, • Application Notes and Design Notes, • White Papers and Reference Designs, • Mentor junior applications engineers and contribute to best practices for lab methodology and documentation, • Represent the applications team in technical reviews, customer meetings, and internal design discussions Minimum Qualifications • Bachelors degree in Electrical Engineering, ECE, or related field, • 6+ years of experience in power electronics or semiconductor applications engineering, • Strong hands-on experience with DC/DC buck converter design and analysis, • Proven expertise in schematic capture and PCB design using industry-standard tools (e.g., Altium, Cadence, OrCAD, or equivalent), • Extensive lab experience with power measurement, debugging, and validation using oscilloscopes, electronic loads, network analyzers, and power analyzers, • Demonstrated ability to debug complex hardware issues at the device and system level, • Strong technical writing skills with experience producing customer-facing technical documentation, • In-depth understanding of customer product development cycles and manufacturing requirements Preferred Qualifications • Masters degree in Electrical Engineering or related field, • Experience with silicon validation and post-silicon debug of power management ICs, • Strong background in control loop stability, compensation design, and small-signal analysis, • Experience with EMI/EMC mitigation and compliance strategies, • Prior customer-facing or Field Applications Engineering (FAE) experience, • Experience mentoring or leading technical teams Key Competencies • Deep lab-centric problem solving and analytical skills, • Ability to independently drive complex debug and validation efforts, • Strong communication skills bridging customers, applications, and IC design teams, • Technical leadership and ownership mindset

Job Description About Ceribell Ceribell is a medical technology company focused on transforming the diagnosis and management of patients with serious neurological conditions. The Ceribell System is a novel, point-of-care electroencephalography ("EEG") platform specifically designed to address the unmet needs of patients in the acute care setting, and is being used in hundreds of community hospitals, large academic facilities and major IDN's across the country. Our entire team is driven by a shared commitment to transforming the landscape of critical care through our rapid seizure detection technology, come join the movement! Position Overview: We have an exciting opportunity for an FP&A Manager to join our finance team, reporting to the VP of FP&A. The key to your success in this role is the ability to work cross-functionally and to build successful partnerships across the organization. This individual will be required to collaborate across all departments and will have direct exposure to the leadership team. Projects will require strategic thinking, analysis, modeling and building recommendations for senior leadership. Reporting is a critical element of the role and must be handled with extreme integrity. The ideal applicant will have a background in Investment Banking, Private Equity and/or startup strategic finance and business operations. This position has been designated as hybrid, generally contributing from the office in Sunnyvale a minimum of two days per week. What you'll do: • Build and own a scalable FP&A framework that supports Ceribell's growth, operating cadence, and long-term strategic goals, • Improve forecast accuracy and financial visibility across headcount, operating expenses, capital expenditures, and cash flow, • Enable more confident decision-making by delivering clear insights, scenarios, and trade-off analyses to senior leaders, • Strengthen cross-functional financial partnerships, helping leaders understand performance drivers and manage their businesses effectively, • Effectively partner with accounting teams to optimize close and BVA processes, • Elevate the quality and clarity of executive and Board-level financial reporting and storytelling, • Establish consistent, data-driven KPIs and dashboards that connect financial results to operational performance, • Identify and surface risks and opportunities early, enabling proactive course correction, • 8+ years of progressive experience in FP&A, corporate finance, or related roles ideally in a Med Tech environment, • Prior experience in high-growth, public company environments strongly preferred, • Strong financial modeling, forecasting, and analytical skills, • Proven ability to influence and partner with senior leaders across functions, • Experience improving or implementing FP&A processes, tools and systems (NetSuite experience is a plus), • Excellent communication skills with the ability to translate complex data into clear, actionable insights at all levels of an organization In addition to your base compensation, Ceribell offers eligible employees the following: • Performance-based incentive compensation (varies by role), • Equity opportunities, • 100% Employer paid Health Benefits for Employees, • 50% - 70% Employer paid Health, Dental & Vision for dependents (depending on plan selection), • 100% paid Life and Long-Term Disability Insurance, • 401(k) with a generous company match, • Employee Stock Purchase Plan (ESPP) with a discount, • Monthly cell phone stipend, • Flexible paid time off, • 13 Paid Holidays + 3 Company Wellness Days, • Excellent parental leave policy, • Fantastic culture with tremendous career advancement opportunities Equal Opportunity Employer Ceribell is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex (including pregnancy, childbirth and related medical conditions), sexual orientation, gender identity or expression, national origin, age, marital status, disability, veteran status or any other characteristic protected by law. Any applicant with a disability who requires an accommodation during the application process should contact to request reasonable accommodation. Privacy Statement For information on how Ceribell processes personal data of job applicants, please review our Privacy Policy. Compliance Disclaimer If you believe this job posting is non-compliant, please submit a report to . Please note that we will not respond to inquiries unrelated to job posting compliance.

Job DescriptionLumotive is pioneering the era of programmable optics—where light is controlled as intelligently and flexibly as software. At the heart of this transformation is a once-in-a-generation innovation: a flat CMOS-based “general purpose optic.” Lumotive’s Light Control Metasurface (LCM™) beam forming chips can be programmed to function as a beam steering mirror, a lens, mirror, a beam splitter—or any optical function—replacing bulky and mechanical optical components with a fully digital, reconfigurable semiconductor . This breakthrough lays the foundation for a massive shift in multiple technologies—from 3D sensing and imaging to optical networking, free space optical communication, and beyond. Like the shift from analog to digital in electronics, programmable optics will reshape industries from robotics, self-driving cars, AI, defense, and healthcare. Lumotive’s first commercial application is in LiDAR, where its software-defined beam steering chips are already enabling compact, high-performance, solid-state sensors. These sensors are being deployed today in smart infrastructure, robotics, and mobility systems through leading module makers and solution integrators. With more than 200 patents and growing commercial traction, Lumotive is delivering the world’s first digital platform for light—and redefining what’s possible in the optical age. Job Description: Lumotive is seeking a highly experienced and hands-on Director of Analog to lead the development of next-generation analog circuitry for Beam steering mixed-signal ASIC controllers. This leadership role is critical in defining and driving the development of active transistor matrix arrays and analog channel driver technologies in close collaboration with optical and ASIC design teams.You will oversee the full life cycle of mixed-signal IPs—from architecture definition, design, and layout to tape-out, silicon bring-up, and mass production. This role requires a seasoned technical leader with deep domain expertise, exceptional problem-solving skills, and the ability to thrive in a fast-paced, interdisciplinary environment. You will oversee the full life cycle of mixed-signal IPs—from architecture definition, design, and layout to tape-out, silicon bring-up, and mass production. This role requires a seasoned technical leader with deep domain expertise, exceptional problem-solving skills, and the ability to thrive in a fast-paced, interdisciplinary environment.Responsibilities: • Lead the architecture, design, and development of analog and mixed-signal IPs for beam steering applications., • Collaborate with cross-functional teams including optics, digital/ASIC, packaging, and testing to ensure robust integration of analog systems., • Drive the design and optimization of key functional blocks such as DACs, ADCs, LDOs, row/column drivers, and output buffers., • Oversee simulations, physical implementation, tape-out, and bring-up of mixed-signal ICs., • Provide hands-on technical guidance and mentorship to the analog design team., • Interface with foundry partners to evaluate and select optimal CMOS process nodes., • Ensure successful silicon validation and characterization through lab measurements and debugging., • Contribute to the development and execution of the technology roadmap for analog and mixed-signal IP.Qualifications:, • PhD or MS in Electrical Engineering or related field with 10+ years of experience in analog and mixed-signal IC design., • Proven track record of delivering first-pass functional silicon for complex mixed-signal ASICs, especially in CMOS technologies optimized for image sensors or display drivers., • Deep understanding of analog display driver circuits including active-matrix architectures, row/column drivers, DAC/ADC design, LDOs, and output buffers., • Strong expertise in low-power, high-precision analog design techniques., • Hands-on experience with transistor-level design tools (e.g., Cadence Virtuoso, AMS design flows)., • In-depth knowledge of process technology and device physics, preferably from leading foundries., • Proficiency in lab testing and silicon debugging using oscilloscopes, spectrum analyzers, signal generators, etc., • Experience with active-matrix display systems and analog circuit characterization., • Exceptional communication skills, both verbal and written, with the ability to present complex technical concepts clearly., • Demonstrated leadership in managing and mentoring high-performing analog design teams., • Experience in high-volume production and yield optimization of analog/mixed-signal chips.

Job DescriptionReady to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life. We are looking for a highly skilled Senior Analog IC Layout Design Engineer to join our dynamic team. The ideal candidate will have extensive experience in designing and optimizing the layout of analog and mixed-signal integrated circuits (ICs). You will work closely with circuit design engineers to translate schematics into high-performance, manufacturable layouts, ensuring adherence to design rules and specifications.What you will do: • Perform full custom analog and mixed-signal IC layout design, including floor planning, placement, and routing of circuits such as amplifiers, data converters, voltage regulators, and RF components, • Collaborate closely with circuit design engineers to understand design specifications and ensure high-performance layout implementations, • Optimize layouts for performance metrics such as area, power, noise, parasitics, and matching, • Perform DRC (Design Rule Check), LVS (Layout Versus Schematic), and parasitic extraction using industry-standard tools (e.g., Cadence Virtuoso, Mentor Graphics Calibre), • Conduct peer reviews of layout work, provide feedback, and mentor junior layout engineers, • Work with process and foundry engineers to understand and integrate process limitations and requirements into the layout design, • Ensure designs meet manufacturability standards and participate in post-layout simulation and validation, • Develop and maintain layout methodologies and documentation for efficient and consistent design practicesWhat you bring to this role:, • 7+ years of experience in custom analog IC layout design, • Strong proficiency in using CAD tools for layout design (e.g., Cadence Virtuoso, Mentor Graphics Calibre, Synopsys IC Compiler, etc.), • Extensive experience with analog layout techniques for minimizing noise, matching, and parasitic effects, • Deep understanding of semiconductor process technologies and design rules, • Proven track record of successful tape-outs of complex analog/mixed-signal ICs, • Excellent attention to detail and a methodical approach to design and validation, • Strong communication skills and ability to work effectively in cross-functional teamsBonus points for the following:, • Bachelor’s or Master’s degree in Electrical Engineering, Microelectronics, or a related field, • Experience with RF IC layout design, • Familiarity with scripting (e.g., Skill, Python) to automate layout tasks and improve productivity • An opportunity to really make a difference• Sustainability at our core• Fair and honest workplace• Innovative thinking is encouraged• Competitive salaries• Continuous learning and development• Health and wellness care options• Financial solutions for the future • Optional legal services (US only)• Paid holidays• Paid time off

Job DescriptionSalary: $130k 150k DOE AboutKnightscope (LEAVE AS IS) Knightscope is a security technology company building the Nations First Autonomous Security Force. The Company combines autonomous machines, advanced software, and human expertise to help protect people, property, and critical infrastructure. Knightscopes long-term mission is to make the United States of America the safest country in the world Job Summary Knightscope is seeking a Corporate Communications Manager to lead our corporate communications function across investor relations, media relations, executive communications, and internal employee communications. About the Role This role owns how the company communicates to investors, media, employees, and the broader market. As a publicly traded company operating in the physical security sector, disciplined, strategic, and compliant communication is essential to maintaining credibility and supporting long-term growth. Key Responsibilities Investor Relations & Public Company Communications • Own and maintain the investor relations website, ensuring accuracy, compliance, and professionalism, • Draft and coordinate earnings press releases and supporting materials, • Assist in preparation of executive scripts and remarks for earnings calls and investor presentations, • Draft shareholder communications and investor updates, • Coordinate distribution of material announcements in partnership with finance and legal, • Ensure alignment across press releases, investor materials, and public disclosures Media & Public Relations • Draft and distribute press releases across corporate milestones, partnerships, product announcements, and financial updates, • Build and maintain targeted media relationships across industry and business outlets, • Manage inbound media inquiries and coordinate interviews, • Proactively identify and pursue media opportunities, • Monitor coverage, sentiment, and share of voice Executive Communications • Draft talking points, prepared remarks, briefing documents, and executive messaging, • Support CEO and leadership visibility through strategic communication planning, • Prepare executives for media interviews, investor discussions, and public appearances, • Ensure executive messaging aligns with company strategy and disclosure requirements Internal Communications • Develop and manage company-wide communications and leadership updates, • Support town halls, major announcements, and organizational communications, • Build a consistent internal communication cadence as the company scales, • Ensure alignment and clarity during high-impact company moments Corporate Narrative & Modern Communication Channels • Define and refine Knightscopes corporate narrative across all audiences, • Ensure consistency across websites, investor materials, press releases, executive messaging, and digital channels, • Support strategic messaging across digital platforms including websites, social channels, and executive profiles, • Translate complex financial and technical information into clear, accessible communication, • Incorporate visual and digital elements into communication strategies where appropriate Crisis & Issues Management • Develop and draft reactive statements when necessary, • Support coordinated communication during sensitive or high-visibility situations, • Monitor media and public sentiment for reputational risk Required Qualifications • 10+ years of experience in corporate communications, public relations, or investor relations, • Direct experience in a publicly traded company is required, • Demonstrated ownership of corporate communications programs, not just tactical support, • Exceptional writing, editing, and executive communication skills, • Proven ability to communicate complex financial, operational, and technical topics clearly, • Experience working directly with executive leadership, • Strong understanding of disclosure best practices and public company communication standards, • Ability to manage confidential information with discretion and sound judgment, • Comfortable operating independently while collaborating across departments Compensation & Benefits • Base Salary:$130k 150k DOE, • Equity:Stock options, • Benefits:Medical, dental, vision, 401(k), paid time off, • Location Requirement:Full-time, on-site at Sunnyvale HQ

Job DescriptionRole Overview The Offline Retail Account Manager is a senior individual contributor responsible for owning revenue, profitability, and execution across major U.S. brick-and-mortar retail partners. This role focuses on in-store retail as the primary growth driver, while ensuring strong alignment with retailer.com and internal global operations. This position requires a high-ownership mindset, strong retailer relationships, and the ability to independently drive results across complex, cross-functional, and cross-border environmentswithout direct people management responsibility. Key Responsibilities Omni-Channel Account Ownership & Revenue Growth • Own revenue, margin, and overall account performance across in-store and retailer.com channels, with in-store as the primary growth driver., • Develop and execute annual and quarterly Joint Business Plans (JBPs), including assortment strategy, pricing, promotions, and merchandising priorities., • Identify growth opportunities and drive execution across distribution expansion, assortment optimization, merchandising, and promotional programs., • Track and manage KPIs including sales, margin, POS/sell-through, distribution, inventory, and promotional effectiveness; course-correct quickly based on performance.Retailer Relationship Management, • Serve as the primary day-to-day owner of retailer relationships, including buyers, category management, demand planning/replenishment, and retail operations (e-commerce partners as needed)., • Lead line reviews, QBRs, and regular business reviews, delivering clear, data-driven insights and recommendations., • Negotiate and secure outcomes in distribution, shelf placement, merchandising, and promotional support., • Represent the company with a high level of credibility, accountability, and commercial judgment.Cross-Functional & Global Collaboration, • Drive alignment across internal partners including Product, Marketing, Finance, and Operations, influencing without formal authority., • Work closely with the overseas offline retail sales operations team on:, • Forecasting and demand planning, • Inventory and replenishment planning, • Performance reporting and KPI tracking, • Day-to-day execution and issue resolution, • Establish clear operating cadence, workflows, and KPIs across time zones.Qualifications Required • 5+ years of experience managing offline retail key accounts across major national retailers (e.g., Walmart, Target, PetSmart, or comparable)., • Proven success driving revenue growth and profitability through distribution expansion, assortment optimization, merchandising, and promotional execution., • Experience working directly with retailer buyers and demand planning / replenishment teams., • Strong analytical skills including POS/sell-through analysis, forecasting, inventory management, and performance reporting., • Excellent communication, negotiation, and presentation skills., • Ability to operate independently, manage ambiguity, and influence cross-functional and global stakeholders., • Comfortable collaborating across multiple time zones.Preferred, • Experience managing omni-channel performance, including collaboration with retailer e-commerce teams., • Category experience in pet, durable goods, small appliances, consumer electronics, or connected devices., • Background from consumer brands, retailers, or manufacturer rep organizations. Your base salary will be within the range of $120,000 to $175,000 USD per year, paid in accordance with the Companys standard payroll practices and subject to applicable withholdings. The specific base salary offered is determined based on a number of factors, including but not limited to geographic location, relevant experience, demonstrated skills and qualifications, internal equity, and current market conditions. You may also be eligible to participate in the Companys annual performance-based incentive program, subject to the terms and conditions of the applicable plan in effect at the time of payout. Participation and any potential payout are not guaranteed and may be modified or discontinued at the Companys discretion. This is a remote position.

Job DescriptionJOB TITLE: PCB DESIGN ENGINEERLOCATION: San Jose, CA • . MUST HAVES:, • Bachelor's degree in electrical engineering, • 5+ years PCB Design Experience with significant portion involving analog and mixed-signal PCB design, and interfacing with PCB Fab houses to improve manufacturability., • Working knowledge in netlisting, schematics usage, electrical and routing rules creation (constraint manager), signal and power integrity optimization, • High proficiency in PADS PCB, Cadence Allegro and scripting using VB and SKILL, • Detail oriented, consistently meeting committed project deadlines, • A strong leader to perform as an individual contributor as well as a project team leader, • Good communicator, written and verbal, using English, • Computer proficiency (Excel), • Related experience in a semiconductor testing environment, ATE industry is preferred, • Experience using Cadence Design Entry HDL or other similar schematics tools (APD, Mentor tools like DX Designer, Expedition) a plusDAY TO DAY:, • Create netlist and routing rules (logical Design) from customer provided information packages and schematics), • Execute physical layout of PCB and substrates (parts placement, routing, trace length adjustment, verification etc.), • Apply electrical design concepts’ knowledge (high-speed design, RF, and power) to meet project requirements, • Design for manufacturability – working with PCB/Substrate suppliers, apply best industry practices to reduce cost and maximize PCB yield., • Verification for new internal design tools and feedback to development team, • Develop design processes to reduce design cycle-time and defects and improve product performance., • Define, create and specify design automation tools., • Create design documents and training., • Develop and lead a team for production design process. This position will own the design process for production. Must be capable to meet quality and lead time objectives., • Capable to utilize multiple time zone design team to meet lead time objectives.

Job DescriptionSenior analog/mixed-signal design engineer focusing on automation of high-performance analog-to-digital and digital-to-analog converters. The successful candidate in this role will be a member of the Automation Compiler Team, focused on innovation and inventing methodologies to automate and parameterize existing IP of high performance transistor level design. This candidate should have some coding background as well, preferably Python and or Skill, and should be able to both understand mixed-signal designs and lead the compiler team to transform a manual design into a parameterized representation that can be used in multiple scenarios. Qualifications • 5+ years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes, • Thorough familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design techniques. Experience in designing high performance building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL etc., • Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis, • Experience with analog and digital behavioral modeling, and/or synthesis of digital control blocks, • Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools, • Familiar with designing circuits for electromigration and ESD compliance in submicron CMOS process, • Must be able to work independently as well as within a team., • Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations, • Automate and parameterize existing high-performance transistor-level IP designs., • Work as a member of the Automation Compiler Team, driving innovation., • Lead the effort to transform manual designs into parameterized representations for versatile use., • Utilize coding skills, preferably in Python and/or Skill, to help the compiler team achieve automation goals., • Strong motivation for innovation and continuous improvement in automation processes., • Strong analytical and problem-solving skills

Job Description Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities. What You'll Do We are looking for a passionate and experienced Staff Engineer, SRAM Circuit Design to lead the development of next-generation SRAM solutions. In this leadership position, you will drive end-to-end design of high-performance, low-power memory circuits used in cutting-edge semiconductor products. Your work will directly influence the power, performance, and area (PPA) efficiency of future computing, mobile, and AI platforms. This role combines deep technical expertise with strategic team leadership, offering the opportunity to innovate at the forefront of semiconductor design. • Design and develop SRAM memory arrays, including bit cells, sense amplifiers, decoders and control circuits for advanced process nodes (e.g., 2nm, 3nm and 5nm)., • Optimize SRAM designs for performance, power and area (PPA) and yield., • Develop custom layouts and perform physical design verifications (e.g., DRC, LVS)., • Evaluate trade-offs between speed, power, and area to meet design targets., • Develop and improve SRAM design methodologies, including automation scripts for design, simulation, and verification., • Work with product and test engineers to develop test plans and support silicon bring-up., • Mentor Junior engineers, providing guidance on SRAM design techniques and best practices., • Perform extensive circuit simulations using tools like HSPICE, finesim or cadence Spectre to validate SRAM functionality and performance., • Bachelor's degree in electrical engineering with 10+ years of industry experience or master's degree in electrical engineering with 8+ years of experience strongly preferred., • Prior experience in SRAM or memory circuit design, with a proven track record of delivering SRAM designs in advanced process nodes., • Strong understanding of semiconductor devices physics and process technology (FinFET, GAA, SOI, etc.)., • Expertise in SRAM architecture, including bitcells, sense amplifiers, write drivers, and read/write control paths., • Familiarity with timing analysis, power analysis, and design for manufacturability (DFM)., • Proficiency in circuit simulation, variation analysis, and design tools such as Spectre, HSPICE, Cadence Virtuoso, etc., • Knowledge of scripting languages (e.g., Python, Perl, TCL) for automation of design tasks., • Strong cross-functional collaboration and communication skills for working with design, layout, verification, and technology development teams., • Experience with advanced technology nodes (e.g., 5nm, 3nm, or beyond)., • Knowledge of SRAM compiler development and experience with low-power SRAM design techniques (e.g., power gating, voltage scaling)., • Background in silicon debug and root-cause analysis. #LI-SF1 What We Offer The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community. Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge. Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies. Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are. Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier. Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you. Base Pay Range$163,000—$253,000 USD Equal Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate's genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Applicant Privacy Policy

Job Description At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape. We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing. About the Role You will join the System on Chip (SoC) Design Team at SK hynix memory solutions America, a group dedicated to delivering best-in-class controllers for high-performance SSDs. This team spans the full design cycle—from micro-architecture and RTL design to timing closure and tapeout readiness—enabling next-generation enterprise and AI data center storage solutions. As a Senior Principal Engineer, you will own critical IP blocks end-to-end, drive methodology improvements (such as AI-assisted design flows), and mentor staff engineers to ensure first-pass silicon success. Responsibilities • Lead End-to-End IP Ownership: Architect, design, and verify complex IP blocks or subsystems for high-performance memory controllers, taking ownership from specification to tapeout., • RTL Design & Integration: Develop efficient, high-speed RTL (Verilog/SystemVerilog) for critical modules, ensuring optimization for power, performance, and area (PPA)., • Design Verification & Quality: Oversee design reviews, linting, Clock Domain Crossing (CDC) analysis, and power analysis to ensure robust functional and timing closure., • Cross-Functional Leadership: Collaborate deeply with verification, DFT, physical design, and firmware teams to resolve complex system-level bottlenecks and ensure seamless integration., • Methodology Innovation: Drive enhancements in design automation (Python/Tcl/Perl) and best practices for synthesis and static timing analysis (STA) to improve team efficiency., • Education: Bachelor's degree in Electrical Engineering, Computer Engineering, or related field., • Experience: 12+ years of hands-on experience in ASIC/SoC design with a proven track record of successful tapeouts., • Technical Mastery: Expert proficiency in Verilog/SystemVerilog, logic design, synthesis, and STA for high-speed digital circuits., • Tool Proficiency: Strong experience with industry-standard EDA tools (Synopsys/Cadence) for simulation, linting, and CDC analysis., • Advanced Education: Master's or PhD in Electrical Engineering with 8+ years of applicable experience., • Domain Knowledge: Deep understanding of memory controller architectures (PCIe/NVMe, DDR, NAND Flash) or error correction algorithms., • High-Speed Design: Experience designing for high-frequency interfaces or data center/enterprise applications., • Scripting/Automation: Proficiency in Python, Tcl, or Perl for design automation and flow optimization., • Leadership: Previous experience serving as a technical lead or architect for a major subsystem or IP block. Key Projects: • Enterprise SSD Controllers for AI/Data Centers: Designing best-in-class SoCs tailored for high-throughput, low-latency enterprise workloads, crucial for AI training and inference clusters., • Hardware Accelerators for Reliability: Developing dedicated hardware accelerators and AI/ML-based error correction algorithms to automate operations and enhance data reliability without sacrificing power or latency., • Next-Gen Interface Integration: Working on controllers that integrate the latest high-speed protocols (PCIe Gen6/7, UCIe, NVMe) to maximize data transfer rates for "Silicon Skyscraper" 3D-IC architectures. Why Join Us? • Direct Impact on AI Infrastructure: You won't just be designing generic chips; you will be building the storage engines that power the global AI ecosystem. SK hynix is a key player in the AI memory landscape (HBM, eSSD), and your work directly addresses the "memory bottleneck" in high-performance computing., • Stability Meets Agility: We offer the resources and stability of a global semiconductor giant (SK hynix Inc.) combined with the agile, innovation-driven culture of a San Jose R&D subsidiary., • Comprehensive Benefits: 401(k) matching, onsite gym and cafeteria (breakfast/lunch/dinner), and generous health coverage, ensuring you are supported both professionally and personally. COMPENSATION: $ 209,150/yr - $237,100/yr REGARDING COMPENSATION: SK hynix memory solutions America Inc. offers you the opportunity to apply your skills to exciting projects while working with innovative teams. Our compensation package is complimented by a generous benefits package including medical, dental, vision, life insurance and a company 401(k) match, as well as cafeteria, onsite gym and much more. If you are motivated by technical challenges, we offer a collaborative work environment that encourages career growth. The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness

Job Description About Etched Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We’re looking for a Head of Physical Design to lead the end-to-end RTL-to-GDSII path for our next-generation transformer inference ASICs. You’ll own all aspects of physical implementation — from floorplanning and synthesis through P&R and signoff — and lead a world-class team of PD engineers to deliver first-pass silicon that’s fast, reliable, and production-ready. This is a rare opportunity to shape the physical design strategy at a company where timing to market and uncompromising performance are critical to success. Key Responsibilities * Own and optimize all facets of physical design, including floorplanning, placement, CTS, routing, and timing closure for complex AI accelerators * Build and lead a high-performing PD team, including engineers focused on implementation, flows, and signoff * Define and drive physical signoff strategy, ensuring DRC, LVS, ERC, and CDC are achieved with margin * Partner closely with RTL, DV, backend, and methodologies teams to ensure seamless integration and handoff across the stack * Guide block-level and chip-level floorplanning with input on timing budgets, power domains, and interconnect strategy * Drive early architecture and microarchitecture input to reduce rework and enable schedule predictability * Interface with EDA vendors and the foundry to integrate cutting-edge tools, flows, and node-specific optimizations * Lead the development of automation scripts (e.g., Python, Tcl) to accelerate design cycles and increase flow robustness * Create telemetry and dashboards to track design health and ensure accurate KPIs across closure milestones * Deliver fast, production-grade silicon through aggressive, high-confidence planning and execution You may be a good fit if you have * 10+ years of experience in physical design for advanced-node ASICs, including multiple successful tapeouts * Demonstrated ownership of complex block- and full-chip physical implementation projects, from RTL handoff to signoff * Deep expertise in timing closure, including STA, path analysis, constraint management, and ECO optimization * Experience managing and mentoring physical design teams, ideally in fast-paced or startup environments * Strong scripting and automation skills (Python, Tcl) to optimize workflows and improve engineering velocity * Familiarity with leading EDA tools like Cadence Innovus, Synopsys ICC2, and Mentor Calibre * Comfort working in a high-performance, in-person engineering culture that values ambition and execution Benefits * Medical, dental, and vision packages with generous premium coverage * $500 per month credit for waiving medical benefits * Housing subsidy of $2k per month for those living within walking distance of the office * Relocation support for those moving to San Jose (Santana Row) * Various wellness benefits covering fitness, mental health, and more * Daily lunch + dinner in our office How we’re different Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs. We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed. Compensation Range: $200K - $300K

Job DescriptionSenior Digital/Mixed-Signal Design Engineer focusing on high-performance analog-to-digital and digital-to-analog converters. Job responsibilities include development and verification of the digital controller for high performance data converters, behavioral modeling, customer support, and to assist with synthesis and place-and-route flow for the digital controller for high performance data converters.Qualifications • BS + 4 years or equivalent experience in high-performance digital or mixed-signal IC development in advanced CMOS processes, • Deep knowledge of Verilog RTL coding including state machines, adders, multipliers, combinatorial logic, etc, • Strong understanding of digital design for mixed signal control loops and designing Verilog code to control analog circuits (e.g. digital backend for ADC, digital PLL, etc), • Familiarity with behavioral Verilog code, including wreals, • Ability to write thorough testbenches, • Preferred knowledge of synthesis tool, • Basic understanding of SystemVerilog and assertions preferred, • Familiarity with place and route tool flow preferred but not mandatory, • Basic understanding of signal processing – MATLAB understanding would be preferred but not mandatory, • Extensive experience with synthesis flow in nano-meter scale CMOS, • Extensive experience with place and route flow, • Deep understanding of constraints, especially for mixed-signal designs, including multiple clock domains and clock gating, • Familiarity with timing closure and static timing analysis tools, • Experience with scan chain vector generation and verification

Job Description About SiTime SiTime Corporation is the precision timing company. Our semiconductor MEMS programmable solutions offer a rich feature set that enables customers to differentiate their products with higher performance, smaller size, lower power and better reliability. With more than 3 billion devices shipped, SiTime is changing the timing industry. For more information, visit . Responsibilities: • Lead development of analog Mixed-signal IC and owns the top level, • Supervise and review block designer work and hold design review, • Work with cross-functional team to architect the chip for DFT, • Closely work and support cross functional team for bench validation, qualification and final test development., • Develop analog and mixed-signal architectures and circuits in CMOS or BiCMOS processes, • Analyze technology, architecture, circuit design, and parametric design trade-offs to meet aggressive technical performance specifications, • Perform transistor-level design and simulation using industry leading EDA tools, • Lead comprehensive design reviews, • Supervise Analog Circuit Physical Design Layout and edit layouts, • Collaborate with Digital Design Engineers, CAD, Systems Engineering, Test Engineering and Applications teams to ensure DFT, DFM features and achieve rapid silicon bring-up and time to production release, • Work closely with the verification team to define the verification matrix., • Have the ownership of the top-level schematic and run all the top-level analog simulation., • Participate in top-level AMS verification. Qualifications & Requirements : • M.Sc. with minimum 10 years of relevant experience or Ph.D. with 6 years of with relevant experience in Electrical Engineering, • Provel track record of taking at least one analog-mixed signal part to high-volume production., • Proven track record at each stage of the following:, • Circuit architecture development and technical feasibility studies, • Writing detailed block-level specifications and review documents, • Detailed design and simulation of one or more of the following: Oscillators, ADCs, DACs, temperature sensors, Integer and Fractional-N PLLs, Digital PLLs, low-noise op-amps, regulators, bandgap circuits in CMOS or BiCMOS processes, subthreshold circuits and architecture., • Proficiency with EDA tools including Cadence Virtuoso, Spectre, ADE, Mixed-mode AMS tools, Layout XL, • Extensive knowledge of layout effects for circuit and layout design. Ability to supervise layout designers, • Extensive experience with post-layout extraction and verifications, • Experience with validation, characterization, qualification, and adherence to production release criteria, • Ability to communicate and work effectively with geographically dispersed teams of mixed-signal, digital, verifications engineers, • Ability to work independently and drive solutions to challenging problems Desired Characteristics & Attributes: • Strong team player The actual wage offered may vary depending on work location, experience, education, training, external market data, internal pay equity, or other bona fide factors. SiTime compensation packages includes base salary, bonus based on achieving your innovation goals and equity. Benefits offered: 401k plan, health and wellness that includes medical, dental, vision, life, parental leave, legal services, and time off plans. SiTime is an Equal Opportunity Employer. We treat each person fairly and we do not tolerate discrimination or harassment against anyone on the basis of any protected characteristics, including race, color, religion, national or ethnic origin, sex, sexual orientation, gender identity or expression, age, disability, pregnancy, political affiliation, protected veteran status, protected genetic information, or marital status or other characteristics protected by law. SiTime participates in the E-Verify program. Learn More about SiTime: Review the Get to Know SiTime section of our career page to explore our culture, values, and what makes us unique. • Innovation on Top – Philosophies of Innovation with Rajesh Vashist, • Fabrication Knowledge – An Interview with Rajesh Vashist, • SiTime Corporation – YouTube #LI-SITIME

Job DescriptionAHEAD builds platforms for digital business. By weaving together advances in cloud infrastructure, automation and analytics, and software delivery, we help enterprises deliver on the promise of digital transformation. At AHEAD, we prioritize creating a culture of belonging, where all perspectives and voices are represented, valued, respected, and heard. We create spaces to empower everyone to speak up, make change, and drive the culture at AHEAD. We are an equal opportunity employer, and do not discriminate based on an individual's race, national origin, color, gender, gender identity, gender expression, sexual orientation, religion, age, disability, marital status, or any other protected characteristic under applicable law, whether actual or perceived. We embrace all candidates that will contribute to the diversification and enrichment of ideas and perspectives at AHEAD. In this role you will use your business savvy and industry background to help accelerate our AHEAD Cisco Field relationship. You will have the opportunity to drive results and shape the future of our AHEAD partner Cisco relationship across your GEO. As the Sr Channel Manager, you will create GTM Plans, shape strategy, ensure consistent sales contribution, engage in Cisco opportunities in support of our Teams, and drive growth in our Cisco business as well as our strategic relationships with Cisco. Financial / Revenue Track AHEAD’s Cisco Financial objectives: ● Ensure we hit yearly revenue and margin goals ● Yearly MOU tracking/milestones ● Influence MOU investment decisions ● Track pipeline and performance across assigned Geo, ensuring revenue and margin contributions (Contribution from all GEO’s is critical) ● Understanding of VIP and other programs for AHEAD to increase profits Alignment ● Work with Cisco Field, from IC to AVP, in addition to working with local GEO PAM’s to ensure alignment at the field level. ● Develop AHEAD partner QBR messaging for Executive QBR’s and MD QBR’s ● Participate in weekly cadence calls with Cisco / AHEAD Channel team as necessary ● Assist Executives in meetings ensuring we all have the latest news Demand Generation / Pipeline growth ● Develop compelling stitching stories involving Cisco/AHEAD ● Work closely with AHEAD practices - GTM sales plays. ● Ensure consistent win wires and messaging across your Geo ● Monitor a robust sales pipeline and review profitability metrics like overall margin % attainment goals ● Work with the sales teams to drive teaming agreements ● Influence Marketing/DG events, assist in driving attendance The compensation range indicated in this posting reflects the On-Target Earnings (“OTE”) for this role, which includes a base salary and any applicable target bonus amount. This OTE range may vary based on the candidate’s relevant experience, qualifications, and geographic location. Why AHEAD: Through our daily work and internal groups like Moving Women AHEAD and RISE AHEAD, we value and benefit from diversity of people, ideas, experience, and everything in between. We fuel growth by stacking our office with top-notch technologies in a multi-million-dollar lab, by encouraging cross department training and development, sponsoring certifications and credentials for continued learning. USA Employment Benefits include: - Medical, Dental, and Vision Insurance - 401(k) - Paid company holidays - Paid time off - Paid parental and caregiver leave - Plus more! See benefits for additional details.

Job DescriptionAnalog/Mixed-Signal Verification Engineer focusing on high-performance analog-to-digital and digital-to-analog converters. Job responsibilities include the verification of analog and mixed-signal designs for high performance data converters, behavioral modeling, and customer support.Qualifications • 2+ years of experience in high-performance analog or mixed-signal IC development and verification in advanced CMOS processes, • Familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design and building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL etc., • Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis, • Experience with analog and digital behavioral modeling and familiarity with behavioral Verilog / Verilog-A code, including wreals, • Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools, • Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes, • Must be able to work independently, create and adhere to schedules, • Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations

Job Description Job Title: Analog/Mixed-Signal IC Design Engineer Position Type: Full-Time Location: Santa Clara, CA | RTO 5 Days Required Salary Range / Rate: $150k-$250k + Bonus + Stock Option Contact: Key Responsibilities • Lead the design and development of PMIC analog and mixed-signal circuits, with emphasis on multi-face controller implementations., • Architect, design, and optimize DC-DC converters (Buck, LDO) and related power regulation circuits to achieve target specifications in performance, efficiency, and reliability., • Manage the complete IC development cycle: specification, schematic design, simulation, layout review, silicon evaluation, and characterization., • Collaborate closely with international design teams to align requirements, troubleshoot issues, and drive timely delivery of project milestones., • Contribute to system-level design, ensuring robust integration of analog/mixed-signal blocks with digital and control logic., • Provide technical leadership, mentor junior engineers, and foster best practices in design methodology., • Participate in and conduct detailed design reviews, ensuring adherence to quality and reliability standards., • Support lab validation, debug activities, and mass production readiness., • Work with cross-functional teams, including layout, digital design, system architecture, and validation teams, to ensure cohesive project execution., • Continuously explore and adopt advanced analog design methodologies and emerging technologies to maintain competitive technical leadership. Qualifications • MSEE or BSEE (or higher) in Electrical Engineering or related field., • Minimum 8+ years of hands-on analog/mixed-signal IC design experience, with at least 5 years in PMIC design., • Proven track record in multi-face controller design and power management circuits (Buck, LDO, DC-DC)., • Strong knowledge of analog building blocks:op-amps, comparators, bandgap references, oscillators, charge pumps, etc., • Familiarity with mixed-signal interfaces and ADC/DAC integration., • Proficiency in analog circuit simulation and verification tools (Spectre, HSPICE, etc.) and EDA design environments (Cadence, Synopsys, Mentor Graphics)., • Excellent communication skills in English; Mandarin proficiency is a strong advantage., • Ability to collaborate across geographies and lead complex technical discussions., • Demonstrated success in taking designs from concept through to high-volume production., • Familiarity with reliability and qualification processes for semiconductor products. Preferred Skills • Experience in automotive, consumer, or industrial PMIC applications., • Knowledge of EMI/EMC compliance for power systems., • Strong lab skills in silicon validation, debugging, and characterization., • Familiarity with high-volume production flows and reliability/qualification processes., • Hands-on experience with post-silicon bring-up and characterization of mixed-signal ICs. About Us: Founded in 2009, IntelliPro is a global leader in talent acquisition and HR solutions. Our commitment to delivering unparalleled service to clients, fostering employee growth, and building enduring partnerships sets us apart. We continue leading global talent solutions with a dynamic presence in over 160 countries, including the USA, China, Canada, Singapore, Japan, Philippines, UK, India, Netherlands, and the EU. IntelliPro, a global leader connecting individuals with rewarding employment opportunities, is dedicated to understanding your career aspirations. As an Equal Opportunity Employer, IntelliPro values diversity and does not discriminate based on race, color, religion, sex, sexual orientation, gender identity, national origin, age, genetic information, disability, or any other legally protected group status. Moreover, our Inclusivity Commitment emphasizes embracing candidates of all abilities and ensures that our hiring and interview processes accommodate the needs of all applicants. Learn more about our commitment to diversity and inclusivity at . Compensation: The pay offered to a successful candidate will be determined by various factors, including education, work experience, location, job responsibilities, certifications, and more. Additionally, IntelliPro provides a comprehensive benefits package, all subject to eligibility. Powered by JazzHR rJ8mk9rBUl

Job Description We are seeking an experienced SoC Design Verification Engineer with a strong background in UVM-based verification and SystemVerilog to join our dynamic engineering team. The ideal candidate will have hands-on experience in developing and executing complex verification environments, integrating C/C++ models, and debugging issues at both IP and subsystem levels.Key Responsibilities: • Develop, implement, and maintain UVM-based verification environments for SoC and IP-level designs., • Write and execute SystemVerilog assertions to validate design functionality and performance., • Integrate C/C++ reference models within verification testbenches and ensure seamless co-simulation., • Perform debugging at IP and subsystem levels, identifying and resolving functional and timing issues., • Collaborate with design, architecture, and validation teams to define verification plans, strategies, and coverage goals., • Review and analyze waveforms, simulation logs, and coverage reports to ensure thorough verification closure., • Participate in regression management, bug tracking, and documentation for design verification deliverables.Required Qualifications:, • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field., • 10+ years of hands-on experience in SoC or IP-level design verification., • Strong proficiency in SystemVerilog, UVM methodology, and assertion-based verification (ABV)., • Experience integrating C/C++ models in verification environments., • Proven debugging skills at both IP and subsystem levels using industry-standard EDA tools (e.g., Synopsys VCS, Cadence Xcelium, or Mentor Questa).Good to Have:, • Gate-Level Simulation (GLS) and post-silicon verification exposure., • Experience with Low Power Verification (UPF / CPF) methodologies., • Familiarity with ARM-based SoC architectures and interconnect verification. California Pay Range$160,000—$180,000 USD

Job Description About the Role We are looking for a highly experienced Photonics Chip Lead to take ownership of the design and delivery of advanced Photonic Integrated Circuits (PICs) for next-generation optical networking solutions. This role requires deep technical expertise in Silicon Photonics systems, block and device design, as well as proficiency with IC design tools and PIC/ASIC co-design methodologies. You will lead the full lifecycle of photonic chip development—from architecture through physical design and integration—collaborating with multidisciplinary engineering teams. Key Responsibilities * Lead the design and delivery of Photonic Integrated Circuits (PICs) for core product lines. * Drive all key phases of PIC development, including architecture, photonic routing, schematic capture, modeling, and physical layout. * Collaborate closely with analog, digital, and packaging teams to ensure all product and integration requirements are met. * Contribute to the design and optimization of Silicon Photonics devices and subsystems, enhancing the internal photonics design kit (PDK) and design libraries. Qualifications Specialized Skills * Proven experience in end-to-end Silicon Photonics PIC design, including architecture, link budget analysis, and system integration. * Expertise in photonic circuit modeling and simulation using industry-standard tools such as Lumerical, Photon Design, RSoft, or VPI. * Strong background with physical design and layout tools (e.g., Cadence, Mentor Graphics, or equivalent). * Experience in co-designing PICs with ASICs and digital control systems. * Familiarity with data analysis platforms like JMP or DataConductor. Education * Master's degree in Electrical Engineering, Physics, or a related field (Ph.D. preferred). Experience * 10+ years of hands-on experience in Silicon Photonics design and product development. Attributes * Highly self-driven with a proactive and solution-oriented mindset. * Excels in collaborative, fast-paced environments. * Excellent verbal and written communication skills. * Demonstrates strong attention to detail and creative problem-solving ability. California Pay Range$195,000—$235,000 USD

Job DescriptionSalary: $165,000 to $175,000 Role: In your role as a Staff CAD Engineer (Infrastructure), you will support and improve CAD design tool usage and flows. Projects will have high visibility with a world-wide team of development engineers. This position emphasizes EDA compute infrastructure. You will play a critical role in improving the engineering compute infrastructure for efficiency and scalability. Key Responsibilities: • Manage the EDA infrastructure and create/develop system monitors to support custom analog-mixed signal and digital design projects, • Implement best-in-class CAD license and hardware resource monitors., • Develop benchmark and QA systems to qualify flows and to improve datacenter hardware specifications., • Enhance EDA tool performance through optimization of compute (CPU, GPU) and storage architectures., • Develop strategies for using load balancing and methodologies for bursting peak workloads into private cloud datacenters., • Actively participate in CAD infrastructure planning with IT to improve productivity., • Support tool bugs and issues, working closely with world-wide design teams and EDA vendors. Basic Qualifications: • B.S. or M.S. in electrical/computer engineering or related engineering disciplines. Relevant work experience in industry commensurate to the title., • Expert level understanding of Linux system and tools, as well as tcl/csh/bash scripting., • Expertise in Python and Python/Qt GUI programming., • High-level communication and organizational/execution skills to effectively drive CAD projects and priorities with Credo design teams and design tool vendors., • Expertise in Cadence, Siemens, and/or Synopsys EDA tool solutions. Good technical understanding of EDA design flows in one or more of the following areas RC extraction, physical verification, analog simulators (especially for high-frequency RF designs), packaging tools and SI/PI analysis, RTL design/optimization/verification, SOC physical design. Preferred Skills: • Experience in administering load balancing systems like LSF and SGE is a big plus.

Job Description Crusoe is on a mission to accelerate the abundance of energy and intelligence. As the only vertically integrated AI infrastructure company built from the ground up, we own and operate each layer of the stack — from electrons to tokens — to power the world's most ambitious AI workloads. When you join Crusoe, you join a team that is building the future, faster. We're in the midst of the greatest industrial revolution of our time. The demand for AI compute is boundless, and power is a bottleneck. We're solving that — with an energy-first approach that makes AI infrastructure better for the world and faster for the people innovating with AI. We're looking for problem-solving, opportunity-finding teammates with a sense of urgency, who believe in the scale of our ambition and thrive on a path not fully paved — people who want to grow their careers alongside a team of experts across energy, manufacturing, data center construction, and cloud services. If you want to do the most meaningful work of your career, help our customers and partners advance their AI strategies, and be part of a high-performing team that believes in each other, come build with us at Crusoe. About the Role: The Director of Executive Operations will lead Crusoe’s Executive Assistant function, owning the strategy, structure, and effectiveness of executive support across the company. This role is responsible for building a scalable EA operating model, setting clear standards, and developing the EA team to deliver consistent, high-quality support to leaders as Crusoe grows. This position is focused on organizational leadership rather than direct administrative support. The Director will operate as the functional leader for Executive Assistants, defining expectations, improving operating rigor, and ensuring alignment with leadership priorities and company operating cadence. The individual in this role must exercise sound judgment, adapt to varied leadership styles, and bring structure to a fast-moving environment. This is a full-time, on-site position based in San Francisco, Sunnyvale, or Denver. What You'll Be Working On: EA Function Leadership * Lead and manage the EA team, providing clearing direction, coaching, feedback, and professional development. * Own the operating model for executive support across the organization, ensuring clarity of roles, coverage, and service levels. * Create and evolve a framework for EA career progression, skills development, and growth opportunities. * Support workload balancing and ensure the team has clear expectations, processes, and tools. * Build a collaborative EA community with shared best practices and regular team learning sessions. * Foster a strong EA team culture focused on trust, collaboration, learning, and shared accountability. * Drive consistency in how executives engage with and leverage EA support. * Work closely with People and Workplace Operations on staffing plans, hiring, and long-term organizational design for the EA function. * This role requires travel to connect with EAs across locations and develop a strong understanding of our people, teams, and workplaces. Operational Excellence and Systems Development * Evaluate current administrative workflows and implement improvements that increase efficiency and consistency. * Build templates, playbooks, and processes that support a scalable EA model. * Strengthen scheduling norms, communication frameworks, and cross-functional coordination with leaders and departments. * Partner with Workplace Operations leadership on long-term planning for structure, systems, and capabilities within the EA function. * Brings a high level of discretion and professionalism, comfortable operating independently while managing confidential and sensitive information. * Provide oversight and guidance during high-stakes leadership events, planning cycles, and company moments. What You'll Bring to the Team: * 8–12+ years working closely with senior leadership teams, with strong understanding of executive operations. * Demonstrated ability to influence and drive alignment beyond direct reporting lines. * Experience managing or developing a team of EAs or administrative professionals. * Proven ability to build and scale operational frameworks, standards, and service models. * Strong communication skills and ability to create alignment across leadership and support functions. * A structured and pragmatic approach to prioritization and problem solving. * Ability to work on-site five days per week and coordinate across multiple time zones. * Brings a high level of discretion and professionalism, comfortable operating independently while managing confidential and sensitive information. Benefits: * Industry competitive pay * Restricted Stock Units in a fast growing, well-funded technology company * Health insurance package options that include HDHP and PPO, vision, and dental for you and your dependents * Employer contributions to HSA accounts * Paid Parental Leave * Paid life insurance, short-term and long-term disability * Teladoc * 401(k) with a 100% match up to 4% of salary * Generous paid time off and holiday schedule * Cell phone reimbursement * Tuition reimbursement * Subscription to the Calm app * MetLife Legal * Company paid commuter benefit; $300/month Compensation Range Compensation will be paid in the range of up to $168,000 -$228,000 + Bonus. Restricted Stock Units are included in all offers. Compensation to be determined by the applicants knowledge, education, and abilities, as well as internal equity and alignment with market data. Crusoe is an Equal Opportunity Employer. Employment decisions are made without regard to race, color, religion, disability, genetic information, pregnancy, citizenship, marital status, sex/gender, sexual preference/ orientation, gender identity, age, veteran status, national origin, or any other status protected by law or regulation.

Job DescriptionAnalog/Mixed-Signal Design Engineer focusing on high-performance analog-to-digital and digital-to-analog converters. The successful candidate in this role will design high performance transistor level circuits starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market. Qualifications • 2+ years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes, • Familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design and building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL etc., • Must have experience with evaluating silicon on bench and familiarity with standard lab equipment, • Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis, • Experience with analog and digital behavioral modeling, • Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools, • Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes, • Must be able to work independently, create and adhere to schedules, • Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations

Job DescriptionSenior Analog/Mixed-Signal Design Engineer focusing on high-performance analog-to-digital and digital-to-analog converters. The successful candidate in this role will do high performance transistor level design starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market. Qualifications • 5+ years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes, • Thorough familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design techniques. Experience in designing high performance building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL etc., • Must have a track record of successfully taking designs to production, • Must have experience with evaluating silicon on bench and familiarity with standard lab equipment, • Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis, • Experience with analog and digital behavioral modeling, and/or synthesis of digital control blocks, • Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools, • MATLAB understanding would be preferred but not mandatory, • Familiar with designing circuits for electromigration and ESD compliance in submicron CMOS process, • Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes, • Must be able to work independently, create and adhere to schedules, • Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations

Job Description ASIC / VLSI ENGINEERS – STA / Physical Design / Design Verification 3 outstanding, full-time positions have become available; a) STA Engineer, b) Physical Design Engineer, and c) Design Verification Engineer; in the Silicon Valley area for individuals with a minimum of 4+ years of experience in ASIC / VLSI design engineering within advanced semiconductor environments. This opportunity is with a well-established engineering services firm supporting some of the most innovative product companies in the industry with competitive compensation up to $225K DOE and offering strong benefits package and long-term project stability. These are full-time, onsite roles working on advanced chip development programs across multiple client environments. Candidates should have strong experience in one primary specialization area: Static Timing Analysis, Physical Design, or Design Verification. All candidates MUST have the following experiences to qualify for consideration • Experience working in digital design or verification flows (RTL-based development environments), • Understanding of ASIC design lifecycle (synthesis, implementation, or verification depending on role), • Experience with scripting languages such as Python, Tcl, or Perl (or equivalent automation experience), • Strong understanding of digital logic design fundamentals, • Experience working in advanced technology nodes (28nm and below preferred, not required) Candidates should have strong experience in ONE of the following areas Static Timing Analysis Engineer - STA Engineer • Experience performing static timing analysis and timing closure, • Tools such as Synopsys PrimeTime, Cadence Tempus, or equivalent, • Timing constraint development and optimization, • RTL synthesis and timing correlation experience (preferred), • Understanding of Verilog-based design flows Physical Design Engineer - PD Engineer • ASIC physical design including floorplanning, placement, CTS, and routing, • Timing closure, congestion analysis, and optimization, • Power grid design, IR drop analysis, and low-power implementation techniques, • Physical verification and signoff flows (DRC/LVS experience preferred), • Experience with advanced node implementation environments Design Verification Engineer– DV Engineer • RTL verification across full verification lifecycle, • Development of testbenches using SystemVerilog and/or UVM, • Debugging simulation failures and verification environments, • Experience with simulation tools such as Synopsys VCS or equivalent, • Familiarity with standard protocols (AXI, AHB, PCIe preferred) If interested and QUALIFIED, please send resume in Microsoft Word format to: Etech Hi, Inc. is an equal opportunity employer/staffing firm and we are committed to providing a workplace free from harassment and discrimination. We celebrate the unique differences of our employees and candidates because that is what drives curiosity, innovation, and the success of our business. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, gender identity or expression, age, marital status, veteran status, disability status, pregnancy, parental status, genetic information, political affiliation, or any other status protected by the laws or regulations in the locations where we operate. #IND1 #ZR

Job DescriptionAnalog/Mixed-Signal Design Engineer focusing on high-performance analog-to-digital and digital-to-analog converters. The successful candidate in this role will design high performance transistor level circuits starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market. Qualifications • MS or PhD Degree in Electrical Engineering focused on Analog/Mixed-Signal circuit design., • Students who graduated recently or are close to graduation from their PhD program preferred., • Familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design and building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL etc., • Must have experience with evaluating silicon on bench and familiarity with standard lab equipment, • Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis, • Experience with analog and digital behavioral modeling, • Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools, • Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes, • Must be able to work independently, create and adhere to schedules, • Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations

Job DescriptionSerDes analog designer focusing 100Gbps+ wireline technologies (TX and RX path). The successful candidate in this role will develop cutting-edge circuits and architectures for ultra-high speed wireline communication systems, and will drive the development of high performance transistor level design starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market. Qualifications • 10+ years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes, • Familiarity with high-speed analog design and building block circuits for SERDES technology such as ADC/DAC, CTLE, CDR, PLL etc., • Must have a track record of successfully taking designs to production, • Ability to work with customers to define products that address needs, • Must have experience with evaluating silicon on bench and familiarity with standard lab equipment, • Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis, • Experience with analog and digital behavioral modeling, and/or synthesis of digital control blocks, • Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools, • MATLAB understanding would be preferred but not mandatory, • Familiar with designing circuits for electromigration and ESD compliance in submicron CMOS process, • Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes, • Must be able to work independently, create and adhere to schedules

Job Description Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities. What You'll Do As a seasoned Senior Technical Project Manager (ASIC) you will lead complex silicon development projects from specification definition through tape-out, fabrication, and post-silicon validation. You will be the primary face of Samsung's (SLSI's) ASIC design, verification, physical design, firmware, foundry and advanced packaging teams to the customer and ensure the timely delivery of all collateral. This role requires a strong technical background in semiconductors combined with exceptional program management skills to navigate risks and drive execution excellence. Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy. Reports to: Team leader/Head of Custom SoC Solutions Team. Job ID: 42809 Key Responsibilities • End-to-End Program Ownership: Work with customers from initial concept and specification stage to silicon tape-out, bring-up, and production. This includes not only technical, but also spans commercial and legal domains., • Project Planning & Scheduling: Develop and maintain detailed project plans, milestones, and resource allocation. Proactively identify and resolve bottlenecks and critical path issues., • Cross-Functional Coordination: Collaborate with Architecture, RTL, Verification, Physical Design (PnR), DFT, Firmware, Emulation and Packaging teams to ensure aligned deliverables. Participate in cross functional meetings and identify and eliminate bottlenecks., • Education: Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 15+ years or a Master's degree with 13+ years., • Experience: 10+ years in the semiconductor industry, with at least 5+ years in technical program/project management for ASIC/SoC products., • Technical Knowledge: Deep understanding of the full ASIC design flow (RTL, Simulation, Synthesis, STA, PnR, DFT, Tape-out)., • Methodologies: Proven experience working with advanced process nodes and high-speed design., • Tools: Proficiency in project management tools (Jira, Confluence, MS Project) and familiarity with EDA tools (Synopsys, Cadence)., • Experience with complex packaging (2.5D/3D IC, Si interposers, TSV)., • Knowledge of automotive functional safety and other automotive industry requirements, • Experience with hardware emulation platforms (Palladium, Veloce, ZeBu)., • Leadership: Strong ability to influence cross-functional teams without direct authority., • Problem-Solving: Ability to analyze technical problems and drive solutions in a fast-paced environment., • Communication: Excellent verbal and written communication skills, tailoring technical information for various stakeholders., • You're inclusive, adapting your style to the situation and diverse global norms of our people., • An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding., • You're collaborative, building relationships, humbly offering support and openly welcoming approaches., • Innovative and creative, you proactively explore new ideas and adapt quickly to change. #LI-MD1 What We Offer The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community. Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge. Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies. Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are. Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier. Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you. Base Pay Range$189,000—$301,000 USD Equal Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate's genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Applicant Privacy Policy

Job Description About Etched Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary Building cutting-edge model-specific ASICs requires crafting custom infrastructure and toolchains to support ultra-fast, reliable, and scalable development across the stack - from simulation to silicon. We build this infrastructure as software - and we engineer it with the same best practices we apply to our products. We use the same rigor, design discipline, and quality standards and testing as we do to our ASIC, software, and platform. You will lead the development and adoption of next-generation infrastructure tooling, enabling Etched ASIC, Software, and Platform engineers to iterate faster, build more reliably, and push the boundaries of AI performance. This includes building and scaling our hybrid high-performance compute (HPC) cluster, optimized for massively parallel CI, EDA workflows, Emulation, and hardware-aware job execution. You’ll also architect and implement a state-of-the-art observability stack with LLM integration and a strong emphasis on streaming health and performance telemetry, log aggregation, distributed tracing, insight generation, synthetic testing, and smart alerting - across CI pipelines, simulation clusters, and service endpoints. This role demands a strong software engineering mindset, quality instincts, and deep understanding of systems. It’s not just about writing scripts - it’s about writing code that builds and manages infrastructure with precision, repeatability, and intent. Key responsibilities * Architect and Scale Distributed Compute Systems: Design and build the orchestration layers that drive our hybrid high-performance clusters—enabling simulation, synthesis, and continuous integration of AI ASICs at unprecedented scale. * Build Infrastructure-as-Code Systems: Develop and maintain a fully programmable infrastructure control plane to ensure reproducibility, auditability, and rapid iteration across the entire stack. * Optimize End-to-End Developer Experience: Create tools and abstractions that empower engineers to harness massive parallelism without worrying about the underlying complexity.. * Workload Elasticity, Reliability, and Efficiency: Prototype and execute workload orchestration and migration strategies between on-premise and cloud environments, balancing performance, storage availability and replication, uptime, and cost across heterogeneous hardware and compute backends. * Implement real-time telemetry, tracing systems that surface insights from millions of metrics, enabling proactive debugging and system optimization. * Push the Limits of Observability: Build a full observability stack that includes dashboards, alerting, automated responses, and a synthetic testing framework to proactively test infrastructure performance and reliability for various application and data flows, ensuring we remain proactive against issues impacting development and productivity workflows. Representative projects * Design and deploy a fully automated, scalable hybrid HPC cluster, combining bare-metal servers and switches with cloud instances, provisioned through MaaS and orchestrated via SLURM and Kubernetes, optimized for mixed EDA workloads and parallel CI pipelines. * Develop a real-time observability system for ASIC toolchain jobs and distributed builds, integrating Prometheus, Grafana, and VictoriaMetrics with streaming telemetry, tracing, and alerting to detect performance regressions before they hit silicon. * Architect and implement a programmable infrastructure-as-code control plane, using Terraform, Ansible, and Puppet, to version, audit, and redeploy every layer of Etched's development stack with deterministic reproducibility. * Create a zero-downtime interactive development environment that provisions and connects Jupyter and VS Code sessions to GPUs and high-memory nodes via a secure zero-trust network, abstracting away cluster state and machine failures. * Prototype and evaluate dynamic workload migration strategies between on-premise and cloud environments to optimize for latency, reliability, and cost across simulation and synthesis pipelines. * Design a synthetic testing and fault injection framework to validate the behavior of infrastructure under high-load, degraded hardware, and intermittent network partitions - before they happen in production. You may be a good fit if you * Are a systems-minded software engineer who loves building foundational platforms, working close to the metal and cloud, solving high-leverage problems at scale. * Are a deeply technical engineer who treats infrastructure as a software problem - prioritizing clean abstractions, version control,small change lists, easy roll backs, testing, and long-term maintainability over ad hoc configuration. * Have strong programming skills in languages such as Python, Go, Rust, and C++, and are comfortable building production-grade tooling. * Possess expert-level knowledge of Linux, virtualization, containerization, and CI/CD pipelines, with a deep understanding of how to debug, optimize, and scale complex systems. * Are familiar with Infrastructure as Code tools like OpenTofu, Ansible, or Puppet, and enjoy designing declarative, reproducible infrastructure systems. * Understand and use PromQL and other telemetry/query languages and have used LLM to extract insight from real-time metrics, and know how to architect and tune observability stacks. * Have a track record of debugging and resolving difficult hardware-software integration problems across bare-metal systems, networks, and distributed workloads. * Can lead and mentor technical teams, guiding design decisions and helping others develop sound engineering instincts. * Have 8+ years of experience in infrastructure engineering, systems programming, or backend software development - ideally in environments where performance, scale, or hardware interaction mattered. * Are driven by curiosity, take initiative, and have an innate sense of ownership — you thrive in uncharted territory, design for edge cases, and love making systems more powerful, reliable, and elegant. Strong candidates may also have experience with * Familiarity with Bazel build system * Deep understanding of ASIC development flows, especially those involving Synopsys, Cadence, and Verilator, including how EDA tools interact with infrastructure for simulation, synthesis, and verification. * Hands-on experience architecting systems with AWS, GCP, or Azure, including hybrid on-prem/cloud deployments, workload migration strategies, and cloud-native orchestration tooling. * Experience monitoring, provisioning, and debugging bare-metal servers, network hardware, and high-performance storage systems in rack-scale environments. * Comfortable in profiling and optimizing compute environments for single-threaded latency, memory-bound workloads, or I/O throughput, especially in the context of simulation or CI performance. * Proficiency building or operating telemetry systems at scale using Prometheus, Grafana, Loki, VictoriaMetrics, and tools for distributed tracing, log aggregation, and real-time alerting across heterogeneous mediums (SMS, email, push alerts, etc.) Benefits * Medical, dental, and vision packages with generous premium coverage * $500 per month credit for waiving medical benefits * Housing subsidy of $2k per month for those living within walking distance of the office * Relocation support for those moving to San Jose (Santana Row) * Various wellness benefits covering fitness, mental health, and more * Daily lunch + dinner in our office How we’re different Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs. We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed. Compensation Range: $150K - $250K

Job DescriptionDAC architect and development lead focusing on high-performance digital-to-analog converters. The successful candidate in this role will work with customers to understand requirements, and will lead the development of high performance transistor level design starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market. Qualifications • 10+ years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes, • Thorough familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design techniques. Experience in designing high performance building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL etc., • Must have a track record of successfully taking designs to production, • Ability to work with customers to define products that address needs, • Must have experience with evaluating silicon on bench and familiarity with standard lab equipment, • Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis, • Experience with analog and digital behavioral modeling, and/or synthesis of digital control blocks, • Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools, • MATLAB understanding would be preferred but not mandatory, • Familiar with designing circuits for electromigration and ESD compliance in submicron CMOS process, • Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes, • Must be able to work independently, create and adhere to schedules, • Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations

Job Description Job Description: Product Engineer Location: San Jose HiRel Department: Operations Reports To: Product & Test Engineering Manager, Juan Lopez Summary: The Product Engineer for high reliability Hybrid DC-DC converters for Space and Military applications supports the development and production of new devices and takes product engineering responsibility throughout the product life cycle - from development to production ramp-up and qualification. This position will have a direct impact on meeting our productivity targets and our customers’ expectations. Essential Duties & Responsibilities: • Responsible for DC-DC products (documentation, troubleshooting, analysis, and qualification) to meet Production Yield Goals., • Support production by troubleshooting DC-DC Converters, supporting functional tests, and providing trimming process guidance., • Ensure non-conformances are resolved from failure mode to root cause through corrective and preventative action., • Perform analyses (Stress and Thermal Analysis, MTBF –Reliability) as necessary., • Design and develop test hardware, using Cadence Allegro, and perform simulations for analysis., • Support the release of design packages and review customer specification datasheets., • Support external tests, such as vibration and shock, and radiation tests, including Total Ionizing Dose (TID) and Single Event Effects (SEE)., • Develop and implement test fixtures for ATE (Chroma) conversion projects., • Initiate, write & release new test programs to ensure timely new-product release to production., • Perform test validation, improvement, qualification, and release to production per corporate standards and procedures., • Work with operations to identify and document test improvement opportunities., • Support the test engineering and design teams in defining proper test concepts. Other Duties & Responsibilities: • Comply with all safety policies, practices, and procedures., • Comply with all quality and ITAR policies, practices, and procedures., • Build meaningful and productive relationships with internal business partners., • Participate in proactive team efforts to achieve departmental and company goals., • Contribute to building a positive team spirit., • Communicate effectively with all levels of employees., • Protect confidential information by not communicating, disclosing to, or using it for the benefit of 3rd parties., • Maintain the highest degree of honesty and integrity at all times., • Perform other duties as assigned. Page Break Job Qualifications: • Masters/Bachelor’s Degree in Electrical Engineering or related Field., • 5 to 10 years of experience in related product and/or engineering experience., • Strong understanding of electronic engineering principles in areas including analog and digital circuits, power supplies, and DC-DC converters., • Experience in PCB schematic capture tools such as OrCAD / Cadence Allegro., • Basic programming experience programming in C / C++, VBasic or Python, or LabView is a plus., • Hands-on experience performing bench electrical measurements using signal generators, DVMs, oscilloscopes, and spectrum analyzers., • Excellent analytical and problem-solving skills, as well as teamwork capabilities., • Excellent communication skills and ability to interact with multiple stakeholders. Job Skills: • Design tools/fixtures with minimal guidance., • Standard electronic laboratory equipment: (i.e. Oscilloscopes, Pulse/Signal Generators, Parametric Analyzers, Spectrum Analyzers, etc)., • Knowledge in semiconductor manufacturing is a plus., • Fast technical document generation/modification CAD, Excel, and PCB software is a plus., • Knowledge in military standards (MIL-PRF38534, MIL-PRF-38535, MIL-STD-883, JSTD-001) is a plus., • Self-motivated with the ability to align priorities in accordance with business goals and meet deadlines in a fast-paced environment., • Team player who enjoys working with different disciplines., • High-energy, results-focused self-starter., • Strong analytical ability and decision-making., • Ability to exercise flexibility with quickly changing data requests., • Ability to adapt quickly and learn new tasks independently., • Ability to manage competing priorities., • Excellent organization and planning skills., • Effective communication skills (written & verbal). At Micross, our Core Values of integrity, communication, teamwork, quality and execution, self-discipline and accountability are cultivated throughout all levels of the organization. Micross provides a challenging and enjoyable workplace for members and supports the needs of the community. Micross provides competitive benefits including medical, HSA and FSA plans, dental, vision, company paid basic Life Insurance, Employee Assistance Program (EAP), 401k with employer match, paid leave, vacation, holidays, generous tuition assistance, 529 College Savings, Pet insurance, Legal insurance, and a range of well-being programs available. Salary and benefits commensurate with qualifications and experience.

Job DescriptionADC architect and development lead focusing on high-performance analog-to-digital converters. The successful candidate in this role will work with customers to understand requirements, and will lead the development of high performance transistor level design starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market. Qualifications • 10+ years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes, • Thorough familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design techniques. Experience in designing high performance building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL etc., • Must have a track record of successfully taking designs to production, • Ability to work with customers to define products that address needs, • Must have experience with evaluating silicon on bench and familiarity with standard lab equipment, • Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis, • Experience with analog and digital behavioral modeling, and/or synthesis of digital control blocks, • Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools, • MATLAB understanding would be preferred but not mandatory, • Familiar with designing circuits for electromigration and ESD compliance in submicron CMOS process, • Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes, • Must be able to work independently, create and adhere to schedules, • Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations

We are seeking a highly organized and proactive Executive Assistant to provide comprehensive administrative and operational support to senior leadership.This role requires a strategic thinker who can anticipate needs, manage competing priorities, and ensure seamless day-to-day operations in a fast-p

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Additional Jobs (. If you experience difficulty using this s

We are seeking a highly organized and proactive Executive Assistant to provide comprehensive administrative and operational support to senior leadership.This role requires a strategic thinker who can anticipate needs, manage competing priorities, and ensure seamless day-to-day operations in a fast-p

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world's toughest technical challenges, o

Responsibilities include, but are not limited to:.Provide high-level administrative and operational support to executive leadership, including complex calendaring, scheduling, travel arrangements, and expense reporting.Manage end-to-end meeting coordination, including preparing agendas, taking clear

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Additional Jobs (. If you experience difficulty using this s

We are seeking a highly organized and proactive Executive Assistant to provide comprehensive administrative and operational support to senior leadership.This role requires a strategic thinker who can anticipate needs, manage competing priorities, and ensure seamless day-to-day operations in a fast-p

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Driving adoption of Cadence Quantus signoff parasitic extraction and Voltus

Responsibilities include, but are not limited to:.Provide high-level administrative and operational support to executive leadership, including complex calendaring, scheduling, travel arrangements, and expense reporting.Manage end-to-end meeting coordination, including preparing agendas, taking clear