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A leading technology company is seeking a Principal Application Engineer to support customers in Canada with Cadence's Allegro X PCB design platform.

A leading technology company is seeking a highly motivated Sales Executive to join their commercial team.This remote position focuses on building relationships with customers in the drug discovery market, utilizing technical knowledge to drive sales of OpenEye solutions.The role requires 10+ years o

Job DescriptionSenior Analog/Mixed-Signal Design Engineer focusing on high-performance analog-to-digital and digital-to-analog converters. The successful candidate in this role will do high performance transistor level design starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market. Qualifications • 5+ years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes, • Thorough familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design techniques. Experience in designing high performance building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL etc., • Must have a track record of successfully taking designs to production, • Must have experience with evaluating silicon on bench and familiarity with standard lab equipment, • Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis, • Experience with analog and digital behavioral modeling, and/or synthesis of digital control blocks, • Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools, • MATLAB understanding would be preferred but not mandatory, • Familiar with designing circuits for electromigration and ESD compliance in submicron CMOS process, • Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes, • Must be able to work independently, create and adhere to schedules, • Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations

Job DescriptionSenior analog/mixed-signal design engineer focusing on automation of high-performance analog-to-digital and digital-to-analog converters. The successful candidate in this role will be a member of the Automation Compiler Team, focused on innovation and inventing methodologies to automate and parameterize existing IP of high performance transistor level design. This candidate should have some coding background as well, preferably Python and or Skill, and should be able to both understand mixed-signal designs and lead the compiler team to transform a manual design into a parameterized representation that can be used in multiple scenarios. Qualifications • 5+ years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes, • Thorough familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design techniques. Experience in designing high performance building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL etc., • Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis, • Experience with analog and digital behavioral modeling, and/or synthesis of digital control blocks, • Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools, • Familiar with designing circuits for electromigration and ESD compliance in submicron CMOS process, • Must be able to work independently as well as within a team., • Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations, • Automate and parameterize existing high-performance transistor-level IP designs., • Work as a member of the Automation Compiler Team, driving innovation., • Lead the effort to transform manual designs into parameterized representations for versatile use., • Utilize coding skills, preferably in Python and/or Skill, to help the compiler team achieve automation goals., • Strong motivation for innovation and continuous improvement in automation processes., • Strong analytical and problem-solving skills

Job DescriptionAnalog/Mixed-Signal Design Engineer focusing on high-performance analog-to-digital and digital-to-analog converters. The successful candidate in this role will design high performance transistor level circuits starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market. Qualifications • 2+ years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes, • Familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design and building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL etc., • Must have experience with evaluating silicon on bench and familiarity with standard lab equipment, • Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis, • Experience with analog and digital behavioral modeling, • Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools, • Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes, • Must be able to work independently, create and adhere to schedules, • Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations

Job DescriptionSerDes analog designer focusing 100Gbps+ wireline technologies (TX and RX path). The successful candidate in this role will develop cutting-edge circuits and architectures for ultra-high speed wireline communication systems, and will drive the development of high performance transistor level design starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market. Qualifications • 10+ years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes, • Familiarity with high-speed analog design and building block circuits for SERDES technology such as ADC/DAC, CTLE, CDR, PLL etc., • Must have a track record of successfully taking designs to production, • Ability to work with customers to define products that address needs, • Must have experience with evaluating silicon on bench and familiarity with standard lab equipment, • Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis, • Experience with analog and digital behavioral modeling, and/or synthesis of digital control blocks, • Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools, • MATLAB understanding would be preferred but not mandatory, • Familiar with designing circuits for electromigration and ESD compliance in submicron CMOS process, • Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes, • Must be able to work independently, create and adhere to schedules

Job DescriptionAnalog/Mixed-Signal Verification Engineer focusing on high-performance analog-to-digital and digital-to-analog converters. Job responsibilities include the verification of analog and mixed-signal designs for high performance data converters, behavioral modeling, and customer support.Qualifications • 2+ years of experience in high-performance analog or mixed-signal IC development and verification in advanced CMOS processes, • Familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design and building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL etc., • Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis, • Experience with analog and digital behavioral modeling and familiarity with behavioral Verilog / Verilog-A code, including wreals, • Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools, • Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes, • Must be able to work independently, create and adhere to schedules, • Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations

Job DescriptionAnalog/Mixed-Signal Design Engineer focusing on high-performance analog-to-digital and digital-to-analog converters. The successful candidate in this role will design high performance transistor level circuits starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market. Qualifications • MS or PhD Degree in Electrical Engineering focused on Analog/Mixed-Signal circuit design., • Students who graduated recently or are close to graduation from their PhD program preferred., • Familiarity with high-speed, high-resolution analog-to-digital (ADC) or digital-to-analog (DAC) data converter design and building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL etc., • Must have experience with evaluating silicon on bench and familiarity with standard lab equipment, • Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis, • Experience with analog and digital behavioral modeling, • Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools, • Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes, • Must be able to work independently, create and adhere to schedules, • Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations

Job Description We are seeking an experienced SoC Design Verification Engineer with a strong background in UVM-based verification and SystemVerilog to join our dynamic engineering team. The ideal candidate will have hands-on experience in developing and executing complex verification environments, integrating C/C++ models, and debugging issues at both IP and subsystem levels.Key Responsibilities: • Develop, implement, and maintain UVM-based verification environments for SoC and IP-level designs., • Write and execute SystemVerilog assertions to validate design functionality and performance., • Integrate C/C++ reference models within verification testbenches and ensure seamless co-simulation., • Perform debugging at IP and subsystem levels, identifying and resolving functional and timing issues., • Collaborate with design, architecture, and validation teams to define verification plans, strategies, and coverage goals., • Review and analyze waveforms, simulation logs, and coverage reports to ensure thorough verification closure., • Participate in regression management, bug tracking, and documentation for design verification deliverables.Required Qualifications:, • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field., • 10+ years of hands-on experience in SoC or IP-level design verification., • Strong proficiency in SystemVerilog, UVM methodology, and assertion-based verification (ABV)., • Experience integrating C/C++ models in verification environments., • Proven debugging skills at both IP and subsystem levels using industry-standard EDA tools (e.g., Synopsys VCS, Cadence Xcelium, or Mentor Questa).Good to Have:, • Gate-Level Simulation (GLS) and post-silicon verification exposure., • Experience with Low Power Verification (UPF / CPF) methodologies., • Familiarity with ARM-based SoC architectures and interconnect verification. California Pay Range$160,000—$180,000 USD

Tax Manager / Senior Tax Manager U.We are seeking a hands-on Tax Manager or Senior Tax Manager to join our fast-growing technology company as a key contributor within the Global Tax Compliance team.This role focuses primarily on U.You will prepare and assist with core U.ASC 740 calculations, and pa

At Cadence, We Hire And Develop Leaders And Innovators Who Want To Make An Impact On The World Of Technology.

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Job DescriptionJob Description Role: Analog and RF layout engineer Work location: Sunnyvale, CA Job Type: Contract Interview: Phone/Skype Job Description: • Minimum 6+ years of experience in Analog and RF layout., • Experience developing and leading complex layout IC for high-speed applications in advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level., • Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys., • Experience with layout of high-performance high-speed analog mixed-signal blocks such Transceivers, CMOS drivers, high-speed Data converters and PLLs., • Experience with floor planning, block level routing and top-level chip assemble., • Knowledge of layout techniques such as floor planning, layer generation, thermal aware layout with consideration for electro-migration. Key Responsibilities: developing and leading complex layout IC for high-speed applications in advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level What are the Mandatory skills and skill proficiencies required for this position? advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level. Experience with floor planning, block level routing and top-level chip assemble. Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys. What are the Optional skills and skill proficiencies for this position? Knowledge of layout techniques such as floor planning, layer generation, thermal aware layout with consideration for electro-migration. Additional Information All your information will be kept confidential according to EEO guidelines.

Job DescriptionSalary: $140,000 - $170,000 Credo is engineering the future of high-speed connectivity for the AI-driven world.With a deeply rooted legacy of innovation and a passion for solving the most complex networking challenges, we deliver industry-leading solutions that power the next generation of cloud, AI, and hyperscale data centers. Credo is pioneering a systems-level approach to connectivity, integrating hardware, software, and architecture to deliver holistic solutions. This strategy not only differentiates us in the market but also creates significant value for our customers by accelerating deployment, improving performance, and reducing complexity across their infrastructure. At Credo, youll be part of a team of world-class technologists and engineers that thrive on pushing the limits of whats possible for some of the worlds most important companies. Our portfolio includes cutting edge solutions including our software,optical DSPs, PCIe/CXL products, SerDes IP, and advanced Active Electrical Cables(AECs) all designed for maximum performance, energy efficiency, and scalability. We foster a culture oftechnical excellence, collaboration, and continuous learning, where your ideas can shape the future of connectivity. From silicon architects to systems engineers, every role at Credo contributes to solving real-world problems at scale. Join us and help us architect the next generation of disruptive networking technologies because at Credo, We Connect. About the Role As a Senior Physical Design Engineer, you will manage all aspects of physical design and implementation for Credo SoC designs. This role involves close collaboration with the local frontend team and PD/integration teams in China and Taiwan to ensure successful tapeouts. Responsibilities • Lead and drive top-level, IP, and block-level physical implementation from RTL to GDSII., • Focus on timing, power, and area (PPA) optimization for high-speed SerDes and interconnect subsystems., • Establish and maintain physical design methodologies, flow automation, chip floorplanning, power/clock distribution, chip assembly, P&R, and timing closure., • Perform static timing analysis, power and noise analysis, and physical verification., • Collaborate closely with frontend and integration teams to ensure successful tapeouts. Basic Qualifications • BS/MS in EE/CS with 10+ years of hands-on experience in back-end physical design and verification. Familiar with hierarchical physical design strategies, methodologies., • Proven track records of handling chip level P&R independently and taping out complex SOC chips under tight schedule pressure., • Experience with 5nm and lower technology nodes., • Proven track records of handling chip level P&R independently and taping out complex SOC chips under tight schedule pressure., • Strong proficiency with EDA tools such as Cadence Innovus and Synopsys Fusipn Compiler., • Solid knowledge on static timing analysis (PrimeTime/Tempus), EM/IR-Drop/crosstalk analysis (PTSI/Voltus/Redhawk), extraction (Quantus/StarRC). Preferred Qualifications • Familiarity with DRC, Antenna, LVS, ERC tools like Calibre. The base salary range for this position is $140,000 $170,000 a year. The base salary ultimately offered is determined through a review of education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits. Credo is an Equal Opportunity Employer. We are committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email .

Job DescriptionSalary: $130k 150k DOE AboutKnightscope Knightscope is a security technology company building the Nations First Autonomous Security Force. The Company combines autonomous machines, advanced software, and human expertise to help protect people, property, and critical infrastructure. Knightscopes long-term mission is to make the United States of America the safest country in the world Job Summary Knightscope is seeking a Corporate Communications Manager to lead our corporate communications function across investor relations, media relations, executive communications, and internal employee communications. About the Role This role owns how the company communicates to investors, media, employees, and the broader market. As a publicly traded company operating in the physical security sector, disciplined, strategic, and compliant communication is essential to maintaining credibility and supporting long-term growth. Key Responsibilities Investor Relations & Public Company Communications • Own and maintain the investor relations website, ensuring accuracy, compliance, and professionalism, • Draft and coordinate earnings press releases and supporting materials, • Assist in preparation of executive scripts and remarks for earnings calls and investor presentations, • Draft shareholder communications and investor updates, • Coordinate distribution of material announcements in partnership with finance and legal, • Ensure alignment across press releases, investor materials, and public disclosures Media & Public Relations • Draft and distribute press releases across corporate milestones, partnerships, product announcements, and financial updates, • Build and maintain targeted media relationships across industry and business outlets, • Manage inbound media inquiries and coordinate interviews, • Proactively identify and pursue media opportunities, • Monitor coverage, sentiment, and share of voice Executive Communications • Draft talking points, prepared remarks, briefing documents, and executive messaging, • Support CEO and leadership visibility through strategic communication planning, • Prepare executives for media interviews, investor discussions, and public appearances, • Ensure executive messaging aligns with company strategy and disclosure requirements Internal Communications • Develop and manage company-wide communications and leadership updates, • Support town halls, major announcements, and organizational communications, • Build a consistent internal communication cadence as the company scales, • Ensure alignment and clarity during high-impact company moments Corporate Narrative & Modern Communication Channels • Define and refine Knightscopes corporate narrative across all audiences, • Ensure consistency across websites, investor materials, press releases, executive messaging, and digital channels, • Support strategic messaging across digital platforms including websites, social channels, and executive profiles, • Translate complex financial and technical information into clear, accessible communication, • Incorporate visual and digital elements into communication strategies where appropriate Crisis & Issues Management • Develop and draft reactive statements when necessary, • Support coordinated communication during sensitive or high-visibility situations, • Monitor media and public sentiment for reputational risk Required Qualifications • 10+ years of experience in corporate communications, public relations, or investor relations, • Direct experience in a publicly traded company is required, • Demonstrated ownership of corporate communications programs, not just tactical support, • Exceptional writing, editing, and executive communication skills, • Proven ability to communicate complex financial, operational, and technical topics clearly, • Experience working directly with executive leadership, • Strong understanding of disclosure best practices and public company communication standards, • Ability to manage confidential information with discretion and sound judgment, • Comfortable operating independently while collaborating across departments Compensation & Benefits • Base Salary:$130k 150k DOE, • Equity:Stock options, • Benefits:Medical, dental, vision, 401(k), paid time off, • Location Requirement:Full-time, on-site at Sunnyvale HQ

Job Description We are looking for a skilled and motivated Electrical Engineer to join our team, who will design, build, and test prototype electrical systems for future consumer wearable experiences. We are looking for a candidate with a broad set of experiences, including digital design, analog/mixed signal design, power systems, wearables, or low power design. Responsibilities ● Designing schematics, completing board layouts, assembling, testing, debugging, and integrating designs into electro-mechanical systems. ● Collaborating in a team environment across engineering disciplines. ● Transforming ambiguous requests and vendor reference designs into working custom solutions. ● Incubating new technologies into research prototypes. REQUIRED Qualifications ● 4+ years of experience along with a BS/MS in Digital System Design/Electrical Engineering or Computer Engineering, or equivalent experience. ● Experience with schematic and board design using Cadence Orcad, Altium or equivalent. ● Experience with use of standard electrical engineering tools such as oscilloscopes, high speed digital test equipment, logic analyzers, spectrum analyzers and function generators ● Experience with mixed domain circuit design, filter design, operational/instrumentation amplifiers, ADC/DACs, power supply design, high speed differential circuits, uControllers, uProcessors, and programmable logic based development ● Experience with high speed signaling over DP, MIPI, HDMI, and USB SS Preferred Qualifications ● Familiarity with VR/AR systems or wearable low-power or portable electronic devices.. ● Experience writing scratch or bring-up firmware in C for embedded systems. ● Experience with IMUs/sensor physical sensor systems with an understanding of calibration methods ● Experience defining and coordinating test procedures in a lab and factory environment to facilitate system bring-up and evaluation Experience designing full system prototypes independently

Job Description About Etched Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We are looking for a Signal Integrity and Power Integrity (SI/PI) Engineer to join our platform electrical engineering team. In this role, you will own the SI/PI methodology for high-speed PCB and system designs — from early architecture through final release — ensuring electrical margins are met across interfaces running at multi-gigabit data rates. Key Responsibilities * Perform pre- and post-layout SI simulations for high-speed serial interfaces including PCIe Gen5/Gen6, 112G/224G Ethernet. * Conduct channel analysis and link budget calculations; define topology constraints, trace geometry, stack-up requirements, and via optimization guidelines for PCB designers. * Develop and maintain COM, IBIS, S-parameter, and SPICE models; correlate simulation results against lab measurements. * Execute power delivery network (PDN) design and analysis: target impedance profiling, decoupling capacitor selection, AC/DC power analysis, and IR-drop simulation. * Drive DFI and design rule checks for SI/PI compliance; work with layout teams in Cadence Allegro / Sigrity or Ansys SIwave. * Collaborate with PCB design and layout engineers, and ASIC teams to define and review design guidelines early in the product lifecycle. * Support bring-up, debug signal quality issues, and document root-cause findings with clear corrective actions. * Develop and maintain simulation-to-hardware correlation databases to continuously improve modelling accuracy. You may be a good fit if you have (Must-have qualifications) * B.S. or M.S. in Electrical Engineering or a closely related discipline. * 5+ years of hands-on SI/PI experience on high-speed designs (>1 Gbps serial links or DDR4/5 and HBM3/4 memory interfaces). * Proficiency with industry SI/PI EDA tools (Cadence Sigrity, Ansys SIwave/HFSS, Keysight ADS, or equivalent). * Strong understanding of transmission line theory, return-loss, insertion-loss, crosstalk, eye-diagram analysis, and jitter decomposition. * Experience with PDN modelling, target impedance methodology, and DC IR analysis. * Working knowledge of multi-layer PCB stack-up design and controlled-impedance trace routing. * Hands-on lab skills: S-parameter measurements with VNA, time-domain reflectometry (TDR), BERT operation, and oscilloscope probing techniques Strong candidates may also have experience with (Nice-to-have qualifications) * Prior work in data center, AI/ML accelerator, networking, or high-performance computing (HPC) hardware environments. * Experience scripting automated SI/PI simulation flows using Python or MATLAB to reduce manual simulation turnaround time. Benefits * Medical, dental, and vision packages with generous premium coverage * $500 per month credit for waiving medical benefits * Housing subsidy of $2k per month for those living within walking distance of the office * Relocation support for those moving to San Jose (Santana Row) * Various wellness benefits covering fitness, mental health, and more * Daily lunch and dinner in our office How we’re different Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs. We are a fully in-person team in San Jose and Taipei, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.

Job Description Job Description: Product Engineer Location: San Jose HiRel Department: Operations Reports To: Product & Test Engineering Manager, Juan Lopez Summary: The Product Engineer for high reliability Hybrid DC-DC converters for Space and Military applications supports the development and production of new devices and takes product engineering responsibility throughout the product life cycle - from development to production ramp-up and qualification. This position will have a direct impact on meeting our productivity targets and our customers’ expectations. Essential Duties & Responsibilities: • Responsible for DC-DC products (documentation, troubleshooting, analysis, and qualification) to meet Production Yield Goals., • Support production by troubleshooting DC-DC Converters, supporting functional tests, and providing trimming process guidance., • Ensure non-conformances are resolved from failure mode to root cause through corrective and preventative action., • Perform analyses (Stress and Thermal Analysis, MTBF –Reliability) as necessary., • Design and develop test hardware, using Cadence Allegro, and perform simulations for analysis., • Support the release of design packages and review customer specification datasheets., • Support external tests, such as vibration and shock, and radiation tests, including Total Ionizing Dose (TID) and Single Event Effects (SEE)., • Develop and implement test fixtures for ATE (Chroma) conversion projects., • Initiate, write & release new test programs to ensure timely new-product release to production., • Perform test validation, improvement, qualification, and release to production per corporate standards and procedures., • Work with operations to identify and document test improvement opportunities., • Support the test engineering and design teams in defining proper test concepts. Other Duties & Responsibilities: • Comply with all safety policies, practices, and procedures., • Comply with all quality and ITAR policies, practices, and procedures., • Build meaningful and productive relationships with internal business partners., • Participate in proactive team efforts to achieve departmental and company goals., • Contribute to building a positive team spirit., • Communicate effectively with all levels of employees., • Protect confidential information by not communicating, disclosing to, or using it for the benefit of 3rd parties., • Maintain the highest degree of honesty and integrity at all times., • Perform other duties as assigned. Page Break Job Qualifications: • Masters/Bachelor’s Degree in Electrical Engineering or related Field., • 5 to 10 years of experience in related product and/or engineering experience., • Strong understanding of electronic engineering principles in areas including analog and digital circuits, power supplies, and DC-DC converters., • Experience in PCB schematic capture tools such as OrCAD / Cadence Allegro., • Basic programming experience programming in C / C++, VBasic or Python, or LabView is a plus., • Hands-on experience performing bench electrical measurements using signal generators, DVMs, oscilloscopes, and spectrum analyzers., • Excellent analytical and problem-solving skills, as well as teamwork capabilities., • Excellent communication skills and ability to interact with multiple stakeholders. Job Skills: • Design tools/fixtures with minimal guidance., • Standard electronic laboratory equipment: (i.e. Oscilloscopes, Pulse/Signal Generators, Parametric Analyzers, Spectrum Analyzers, etc)., • Knowledge in semiconductor manufacturing is a plus., • Fast technical document generation/modification CAD, Excel, and PCB software is a plus., • Knowledge in military standards (MIL-PRF38534, MIL-PRF-38535, MIL-STD-883, JSTD-001) is a plus., • Self-motivated with the ability to align priorities in accordance with business goals and meet deadlines in a fast-paced environment., • Team player who enjoys working with different disciplines., • High-energy, results-focused self-starter., • Strong analytical ability and decision-making., • Ability to exercise flexibility with quickly changing data requests., • Ability to adapt quickly and learn new tasks independently., • Ability to manage competing priorities., • Excellent organization and planning skills., • Effective communication skills (written & verbal). At Micross, our Core Values of integrity, communication, teamwork, quality and execution, self-discipline and accountability are cultivated throughout all levels of the organization. Micross provides a challenging and enjoyable workplace for members and supports the needs of the community. Micross provides competitive benefits including medical, HSA and FSA plans, dental, vision, company paid basic Life Insurance, Employee Assistance Program (EAP), 401k with employer match, paid leave, vacation, holidays, generous tuition assistance, 529 College Savings, Pet insurance, Legal insurance, and a range of well-being programs available. Salary and benefits commensurate with qualifications and experience.

Job Description About Etched Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We are seeking a highly skilled and motivated Design For Testability (DFT) Engineer to join our dynamic team. The ideal candidate will be responsible for ensuring the robust testability of integrated circuits (ICs) from the design phase through to production. This role is crucial in improving the efficiency and effectiveness of our testing processes, thereby enhancing overall product quality. Key responsibilities * Develop and implement robust Design for Test (DFT) architectures for ASIC and SoC designs to enhance test coverage, debug capability, and fault isolation. * Integrate industry-standard DFT methodologies such as scan insertion, boundary scan, Built-In Self-Test (BIST), and Memory BIST (MBIST). * Collaborate cross-functionally with design and verification teams to ensure DFT requirements are addressed early and consistently throughout the design cycle. * Analyze test results and silicon debug data to provide design feedback and drive improvements in coverage, yield, and reliability. * Create and execute comprehensive DFT verification plans to validate the correct implementation and functionality of all DFT features. * Apply simulation-based and formal verification techniques to ensure high confidence in DFT logic correctness. * Conduct internal DFT audits and design reviews to proactively identify and resolve gaps in testability or coverage. * Support silicon bring-up, debug, and failure analysis during post-silicon validation to ensure successful product launch. * Partner with test engineering teams to develop and optimize Automated Test Equipment (ATE) programs for volume production. * Generate production-quality test patterns and ensure robust failure analysis capability in high-volume environments. * Collaborate with manufacturing and quality teams to implement data-driven test process improvements and monitor long-term product health. * Ensure test strategies are aligned with product milestones, manufacturing timelines, and quality/reliability targets. * Author and maintain detailed documentation for DFT architecture, test plans, procedures, and debug guides. * Share best practices through training sessions, onboarding, and mentorship to enhance DFT awareness across design and test teams. * Stay current with emerging DFT technologies, industry trends, and evolving standards to continually improve internal methodologies. You may be a good fit if you have * 10+ years of experience in DFT engineering with a track record of successful test implementations for ASIC or SoC products. * A deep understanding of digital design, verification methodologies, and DFT implementation practices. * Proficiency in System Verilog and fluency with industry-standard EDA tools (e.g., Synopsys DFT Compiler, Cadence Encounter Test, Mentor Tessent). * Scripting and automation experience using Python, Perl, or TCL to streamline DFT implementation and test processes. * Track record of leading DFT initiatives across multiple product generations in high-performance or high-volume silicon environments. * Strong analytical and debugging skills, with the ability to work across teams to resolve complex testability issues. * Excellent communication and collaboration abilities, with a focus on clarity and cross-functional alignment. * A Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master’s preferred). Strong candidates may also have experience with * Mixed-signal DFT methodologies and integration of analog testability into SoC workflows. * Industry standards such as IEEE 1149.1 (JTAG), IEEE 1500, and experience applying them in complex designs. * Yield analysis, product engineering, and contributions to test cost reduction and quality improvement programs. Benefits * Medical, dental, and vision packages with generous premium coverage * $500 per month credit for waiving medical benefits * Housing subsidy of $2k per month for those living within walking distance of the office * Relocation support for those moving to San Jose (Santana Row) * Various wellness benefits covering fitness, mental health, and more * Daily lunch + dinner in our office How we’re different Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs. We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed. Compensation Range: $150K - $275K

Job DescriptionCompany Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description Join a team building next-generation flash memory platforms for AI inference, where performance, efficiency, and scalability are being redefined from the ground up. As part of the Emerging Technology Solutions group, we are pioneering new approaches using advanced flash technologies to unlock the next wave of AI performance. This is not an incremental product—it’s an opportunity to work on cutting-edge system architecture, solve first-of-its-kind engineering problems, and directly influence how AI systems are built in the years ahead. ESSENTIAL DUTIES AND RESPONSIBILITIES: You will lead the end-to-end hardware development of advanced storage platforms designed for AI infrastructure • Own full-cycle hardware design from architecture through schematic, layout, bring-up, validation, and qualification, • Drive form factor and PCB design for high-performance systems, including:, • High-speed interfaces, • Power delivery and integrity, • Thermal and mechanical integration, • Work cross-functionally with ASIC, firmware, system architecture, and platform teams to optimize real-world AI workloads, • Develop and execute bring-up, validation, and debug strategies using advanced lab instrumentation, • Solve complex system challenges in:, • Signal and power integrity, • Performance tuning under real workloads, • Reliability and manufacturability, • Lead debug, DOE, and root-cause analysis to push system performance and yield beyond conventional limits, • Partner with manufacturing and supply chain to transition cutting-edge designs into scalable products, • AI-first design – Work on infrastructure purpose-built for AI inference, not legacy systems, • Architectural impact – Influence system-level design decisions, not just component-level execution, • Cutting-edge challenges – Tackle problems where industry solutions are still evolving, • High visibility – Direct impact on strategic products and future technology direction, • End-to-end ownership – From concept to productionQualifications Required • Bachelor’s or Master’s degree in Electrical or Computer Engineering, • 5–10+ years of experience in high-performance hardware design (SSD or related systems), • Strong background in high-speed digital design (PCIe Gen5/Gen6, DDR5, or similar), • Experience with:, • Schematic and PCB design (Cadence Allegro/OrCAD or equivalent), • System bring-up, validation, and debug, • Power delivery and signal integrity considerations, • Proven ability to debug complex system-level issues and drive them to resolution, • Experience with next-generation interconnects (PCIe, CXL, switching architectures), • Exposure to AI, data center, or high-performance compute platforms, • Familiarity with firmware/hardware interaction and system-level optimization, • Background in productization, manufacturing, or OEM enablement Additional Information Sandisk is committed to providing equal opportunities to all applicants and employees and will not discriminate against any applicant or employee based on their race, color, ancestry, religion (including religious dress and grooming standards), sex (including pregnancy, childbirth or related medical conditions, breastfeeding or related medical conditions), gender (including a person’s gender identity, gender expression, and gender-related appearance and behavior, whether or not stereotypically associated with the person’s assigned sex at birth), age, national origin, sexual orientation, medical condition, marital status (including domestic partnership status), physical disability, mental disability, medical condition, genetic information, protected medical and family care leave, Civil Air Patrol status, military and veteran status, or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above. Our non-discrimination policy applies to all aspects of employment. We comply with the laws and regulations set forth in the "Know Your Rights: Workplace Discrimination is Illegal” poster. Our pay transparency policy is available here. Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Based on our experience, we anticipate that the application deadline will be 04/02/2026 (3 months from posting), although we reserve the right to close the application process sooner if we hire an applicant for this position before the application deadline. If we are not able to hire someone from this role before the application deadline, we will update this posting with a new anticipated application deadline. #LI-KH1 Compensation & Benefits Details • An employee’s pay position within the salary range may be based on several factors including but not limited to (1) relevant education; qualifications; certifications; and experience; (2) skills, ability, knowledge of the job; (3) performance, contribution and results; (4) geographic location; (5) shift; (6) internal and external equity; and (7) business and organizational needs., • The salary range is what we believe to be the range of possible compensation for this role at the time of this posting. We may ultimately pay more or less than the posted range and this range is only applicable for jobs to be performed in California, Colorado, New York or remote jobs that can be performed in California, Colorado and New York. This range may be modified in the future., • You will be eligible to participate in Sandisk's Short-Term Incentive (STI) Plan, which provides incentive awards based on Company and individual performance. Depending on your role and your performance, you may be eligible to participate in our annual Long-Term Incentive (LTI) program, which consists of restricted stock units (RSUs) or cash equivalents, pursuant to the terms of the LTI plan. Please note that not all roles are eligible to participate in the LTI program, and not all roles are eligible for equity under the LTI plan. RSU awards are also available to eligible new hires, subject to Sandisk's Standard Terms and Conditions for Restricted Stock Unit Awards., • We offer a comprehensive package of benefits including paid vacation time; paid sick leave; medical/dental/vision insurance; life, accident and disability insurance; tax-advantaged flexible spending and health savings accounts; employee assistance program; other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity; tuition reimbursement; transit; the Applause Program, employee stock purchase plan, and the Sandisk's Savings 401(k) Plan., • Note: No amount of pay is considered to be wages or compensation until such amount is earned, vested, and determinable. The amount and availability of any bonus, commission, benefits, or any other form of compensation and benefits that are allocable to a particular employee remains in the Company's sole discretion unless and until paid and may be modified at the Company’s sole discretion, consistent with the law.

Job DescriptionSalary: $165,000 to $175,000 Role: In your role as a Staff CAD Engineer (Infrastructure), you will support and improve CAD design tool usage and flows. Projects will have high visibility with a world-wide team of development engineers. This position emphasizes EDA compute infrastructure. You will play a critical role in improving the engineering compute infrastructure for efficiency and scalability. Key Responsibilities: • Manage the EDA infrastructure and create/develop system monitors to support custom analog-mixed signal and digital design projects, • Implement best-in-class CAD license and hardware resource monitors., • Develop benchmark and QA systems to qualify flows and to improve datacenter hardware specifications., • Enhance EDA tool performance through optimization of compute (CPU, GPU) and storage architectures., • Develop strategies for using load balancing and methodologies for bursting peak workloads into private cloud datacenters., • Actively participate in CAD infrastructure planning with IT to improve productivity., • Support tool bugs and issues, working closely with world-wide design teams and EDA vendors. Basic Qualifications: • B.S. or M.S. in electrical/computer engineering or related engineering disciplines. Relevant work experience in industry commensurate to the title., • Expert level understanding of Linux system and tools, as well as tcl/csh/bash scripting., • Expertise in Python and Python/Qt GUI programming., • High-level communication and organizational/execution skills to effectively drive CAD projects and priorities with Credo design teams and design tool vendors., • Expertise in Cadence, Siemens, and/or Synopsys EDA tool solutions. Good technical understanding of EDA design flows in one or more of the following areas RC extraction, physical verification, analog simulators (especially for high-frequency RF designs), packaging tools and SI/PI analysis, RTL design/optimization/verification, SOC physical design. Preferred Skills: • Experience in administering load balancing systems like LSF and SGE is a big plus.

Job DescriptionECAD SW Development Engineer (Contract Position) Job TitleECAD SW Development Engineer Job DescriptionThe Apple Hardware Engineering organization is looking for an ECAD development engineer, to develop solutions to improve the efficiency and productivity of the best hardware engineering team on the planet, helping to better realize and deliver Apple’s leading hardware products. With a background in electrical engineering,  PCB design and software development, the ideal candidate will contribute to a large range of projects, focused on PCB design.Responsibility includes but is not limited to enhancing design checking, custom tool application workflows, and the design release process to PLM. The candidate will draw upon strong analysis, communication and problem-solving skills to drive creative, impactful and efficient solutions, helping our hardware design teams deliver their best work. Job ResponsibilitiesDeveloping and testing design tools, workflows, customizations and automationCollaborating with engineering and customer success teamsWorking independently as well as with a larger team EducationBS, MS or equivalent experience preferred Key QualificationsExperience with EDA vendor software - Cadence, Zuken, MentorExpertise in scripting languages - Cadence Skill, Perl, Python, TclComfortable in web development, HTML, CSS and modern Javascript frameworksProficient in SQLExpertise in object-oriented programming and complex data structuresExcellent debugging and critical thinking skills.Excellent analytical and problem-solving skills.Experience delivering customer support and consultationStrong verbal and written communication skills. Preferred Qualifications Proficiency with languages like: Cadence Skill, Perl, Python, JavaScript, Tcl,Proficiency with Linux RHEL3+ years’ experience with configuration management and version control systems, such as Perforce and Git

Job DescriptionCompany Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description ESSENTIAL DUTIES AND RESPONSIBILITIES: • Drive internal tester life cycle development from architecture, design implementation, bring-up, debug, qualification, and release to manufacturing., • Sustaining support for existing tester platforms and field failure support., • Use Cadence/Allegro to capture schematics and guide layout and routing for PCB design. Able to perform PCB layout is a plus, • Write hardware specifications, develop a test plan, and bring up hardware with other teams., • Debug issues in the lab using protocol analyzer and scope., • Plan and execute hardware qualification plans, from early prototypes to mass production., • Proactively identify risks during the development phase and lead mitigation planning., • Improving group working efficiency by initiating and implementing automation through software and tools., • Provide design to the leadership team for making critical decisions related to products, infrastructure, and manufacturing processes.Qualifications REQUIRED: • Experience with high-speed designs such as PCIe, USB, etc…, • Experience with collaborating with other teams such as Manufacturing, Mechanical, Signal Integrity or third-party design house, • Expertise in Board Design using industry standard tool such as Allegro, • Experience with lab bring-up and hardware design validation, • Experience with control interfaces such as SPI, I2C, etc.., • Experience with tackling signal integrity issues and board-mounted power design and distribution techniques, • Experience working with programmable devices such as CPLD & FPGA Additional Information Sandisk is committed to providing equal opportunities to all applicants and employees and will not discriminate against any applicant or employee based on their race, color, ancestry, religion (including religious dress and grooming standards), sex (including pregnancy, childbirth or related medical conditions, breastfeeding or related medical conditions), gender (including a person’s gender identity, gender expression, and gender-related appearance and behavior, whether or not stereotypically associated with the person’s assigned sex at birth), age, national origin, sexual orientation, medical condition, marital status (including domestic partnership status), physical disability, mental disability, medical condition, genetic information, protected medical and family care leave, Civil Air Patrol status, military and veteran status, or other legally protected characteristics. We also prohibit harassment of any individual on any of the characteristics listed above. Our non-discrimination policy applies to all aspects of employment. We comply with the laws and regulations set forth in the "Know Your Rights: Workplace Discrimination is Illegal” poster. Our pay transparency policy is available here. Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution. Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. Based on our experience, we anticipate that the application deadline will be 07/01/2026 (3 months from posting), although we reserve the right to close the application process sooner if we hire an applicant for this position before the application deadline. If we are not able to hire someone from this role before the application deadline, we will update this posting with a new anticipated application deadline. #LI-RT1 Compensation & Benefits Details • An employee’s pay position within the salary range may be based on several factors including but not limited to (1) relevant education; qualifications; certifications; and experience; (2) skills, ability, knowledge of the job; (3) performance, contribution and results; (4) geographic location; (5) shift; (6) internal and external equity; and (7) business and organizational needs., • The salary range is what we believe to be the range of possible compensation for this role at the time of this posting. We may ultimately pay more or less than the posted range and this range is only applicable for jobs to be performed in California, Colorado, New York or remote jobs that can be performed in California, Colorado and New York. This range may be modified in the future., • You will be eligible to participate in Sandisk's Short-Term Incentive (STI) Plan, which provides incentive awards based on Company and individual performance. Depending on your role and your performance, you may be eligible to participate in our annual Long-Term Incentive (LTI) program, which consists of restricted stock units (RSUs) or cash equivalents, pursuant to the terms of the LTI plan. Please note that not all roles are eligible to participate in the LTI program, and not all roles are eligible for equity under the LTI plan. RSU awards are also available to eligible new hires, subject to Sandisk's Standard Terms and Conditions for Restricted Stock Unit Awards., • We offer a comprehensive package of benefits including paid vacation time; paid sick leave; medical/dental/vision insurance; life, accident and disability insurance; tax-advantaged flexible spending and health savings accounts; employee assistance program; other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity; tuition reimbursement; transit; the Applause Program, employee stock purchase plan, and the Sandisk's Savings 401(k) Plan., • Note: No amount of pay is considered to be wages or compensation until such amount is earned, vested, and determinable. The amount and availability of any bonus, commission, benefits, or any other form of compensation and benefits that are allocable to a particular employee remains in the Company's sole discretion unless and until paid and may be modified at the Company’s sole discretion, consistent with the law.

Job Description Who We Are Nuro is a self-driving technology company on a mission to make autonomy accessible to all. Founded in 2016, Nuro is building the world's most scalable driver, combining cutting-edge AI with automotive-grade hardware. Nuro licenses its core technology, the Nuro Driver™, to support a wide range of applications, from robotaxis and commercial fleets to personally owned vehicles. With technology proven over years of self-driving deployments, Nuro gives the automakers and mobility platforms a clear path to AVs at commercial scale, empowering a safer, richer, and more connected future. About the Team The Software Operations team is at the heart of how Nuro's autonomy software gets built right. We own QC, tool testing, and bug reproduction across labeling workflows, and we care deeply about the craft of doing that work well. You'll sit inside the team, learn the work firsthand, and help build the systems that make quality achievable at scale. You'll report directly to the Head of Software Operations with real access, real context, and a genuine mandate to make things better. About the Role This is a 12 month embedded role for someone who loves finding what's broken and fixing it for good. Process improvement should be in your DNA — not a skill you've practiced, but the way you naturally see the world. You'll spend real time inside the in-house team's workflow, then turn what you learn into sharper procedures, cleaner rubrics, and a taxonomy that actually fits the work. You'll also keep our offshore QC vendor team calibrated to the same standards, so the quality holds up wherever the work happens. This role is a great fit if you get energized by noticing what's not working and making a clear case for how to fix it. If you love documentation that's genuinely usable rather than just technically correct, want your work tied directly to a product that matters, and thrive with autonomy and a direct line to leadership, this is the role for you. About the Work Procedures and Rubrics • Turn vague or inconsistent QC procedures into something anyone can execute confidently, • Close the gaps where rubrics meet reality and real-world cases don't fit neatly into the framework, • Audit the classification framework for defects, labeling outputs, and operational findings, • Resolve ambiguity and overlap so the taxonomy reflects how the work actually happens, • Learn the workflow from the inside: tools, handoffs, edge cases, and the friction nobody has documented yet, • Surface patterns only visible up close: the skipped steps, the inconsistent calls, the rubric that doesn't quite fit, • Keep the offshore QC team current on procedures, rubrics, and taxonomy, • Run calibration sessions that close the gap between how standards are written and how they're applied, • Own documentation that is clear, current, and built to outlast any one person, • 4+ years in project management, operations, process design, or QA in a software or tech environment, • A track record of improving procedures, rubrics, or classification frameworks, not just executing against them, • Sharp pattern recognition and the communication skills to turn observations into clear recommendations, • Strong written communication: your procedures and rubrics leave no room for misreading, • Experience in robotics, autonomy, mapping, or visual software environments, • Familiarity with U.S. roadways and driving behavior, • Experience coordinating offshore or distributed contractor teams, • A background in taxonomy, ontology, or classification system design If that sounds like the kind of work you were made for, we'd love to hear from you. At Nuro, your base pay is one part of your total compensation package. For this position the reasonably expected annualized base salary range is $87,000-$118,000. This position is for a 12 month term.Offers are based on an individual's experience, education, location, and skills. At Nuro, we celebrate differences and are committed to a diverse workplace that fosters inclusion and psychological safety for all employees. Nuro is proud to be an equal opportunity employer and expressly prohibits any form of workplace discrimination based on race, color, religion, gender, sexual orientation, gender identity or expression, national origin, age, genetic information, disability, veteran status, or any other legally protected characteristics. #LI-CD1

Job Description Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities. What You'll Do As a seasoned Senior Technical Project Manager (ASIC) you will lead complex silicon development projects from specification definition through tape-out, fabrication, and post-silicon validation. You will be the primary face of Samsung's (SLSI's) ASIC design, verification, physical design, firmware, foundry and advanced packaging teams to the customer and ensure the timely delivery of all collateral. This role requires a strong technical background in semiconductors combined with exceptional program management skills to navigate risks and drive execution excellence. Location: Daily onsite presence at our San Jose headquarters in alignment with our Flexible Work Policy. Reports to: Team leader/Head of Custom SoC Solutions Team. Job ID: 42809 Key Responsibilities • End-to-End Program Ownership: Work with customers from initial concept and specification stage to silicon tape-out, bring-up, and production. This includes not only technical, but also spans commercial and legal domains., • Project Planning & Scheduling: Develop and maintain detailed project plans, milestones, and resource allocation. Proactively identify and resolve bottlenecks and critical path issues., • Cross-Functional Coordination: Collaborate with Architecture, RTL, Verification, Physical Design (PnR), DFT, Firmware, Emulation and Packaging teams to ensure aligned deliverables. Participate in cross functional meetings and identify and eliminate bottlenecks., • Education: Bachelor's degree in Electrical Engineering, Computer Engineering, or related field with 15+ years or a Master's degree with 13+ years., • Experience: 10+ years in the semiconductor industry, with at least 5+ years in technical program/project management for ASIC/SoC products., • Technical Knowledge: Deep understanding of the full ASIC design flow (RTL, Simulation, Synthesis, STA, PnR, DFT, Tape-out)., • Methodologies: Proven experience working with advanced process nodes and high-speed design., • Tools: Proficiency in project management tools (Jira, Confluence, MS Project) and familiarity with EDA tools (Synopsys, Cadence)., • Experience with complex packaging (2.5D/3D IC, Si interposers, TSV)., • Knowledge of automotive functional safety and other automotive industry requirements, • Experience with hardware emulation platforms (Palladium, Veloce, ZeBu)., • Leadership: Strong ability to influence cross-functional teams without direct authority., • Problem-Solving: Ability to analyze technical problems and drive solutions in a fast-paced environment., • Communication: Excellent verbal and written communication skills, tailoring technical information for various stakeholders., • You're inclusive, adapting your style to the situation and diverse global norms of our people., • An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding., • You're collaborative, building relationships, humbly offering support and openly welcoming approaches., • Innovative and creative, you proactively explore new ideas and adapt quickly to change. #LI-MD1 What We Offer The pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community. Enjoy Time Away You'll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge. Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies. Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are. Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier. Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you. Base Pay Range$189,000—$301,000 USD Equal Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate's genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Applicant Privacy Policy

A leading technology company is seeking a Principal Application Engineer to support customers in Canada with Cadence's Allegro X PCB design platform.

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Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is committed to equal employment opportunity throughout all levels of the org

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