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Own Every Moment at NetApp At NetApp, your ideas power innovation. We lead in intelligent data infrastructure—delivering unified storage, integrated data services, and solutions that help organizations unlock the full potential of their data, from AI to multicloud. Ready to innovate and contribute to our path to $10B? Here, you'll collaborate with passionate teams, tackle real-world challenges, and see your impact in how customers transform and grow. If you're ready to bring curiosity, creativity, and drive to every moment, NetApp is where your journey begins. This role is based in the San Francisco Bay Area, and we are only considering candidates who currently reside in the region. Please note that candidates outside of this region will not be considered for this position. We’re expanding our Enterprise Majors organization, a newly created segment focused on serving some of the most strategic, high-value enterprise accounts in the country. These customers are household names in industries like manufacturing, healthcare, automotive, and financial services, companies that depend on data to drive operations, performance, and innovation. Each Solutions Engineer in this segment will be aligned 1:1 with an Enterprise Client Executive, forming a tight two-person team dedicated to driving deep technical engagement, account growth, and long-term success. Together, you’ll build relationships, design complex data solutions, and execute multi-million-dollar strategies for some of the most influential enterprises in the world. • Serve as the technical lead and trusted advisor for a small number of large, strategic enterprise accounts., • Partner closely with your Client Executive to define and execute account strategy, pipeline development, and deal progression., • Build strong relationships with senior architects, IT decision-makers, and technical stakeholders, earning credibility through expertise and trust., • Lead in-depth discovery sessions to uncover pain points and architect end-to-end solutions using the full NetApp portfolio, • Design and position solutions that integrate on-prem, hybrid, and cloud storage architectures to solve complex business challenges., • Support multi-million-dollar sales cycles, often spanning multiple years, while maintaining consistent engagement and technical alignment with the customer, • Collaborate cross-functionally with product management, engineering, and partner teams to ensure seamless execution., • Demonstrate curiosity and initiative, always looking for new ways to add value and drive innovation within your accounts., • A seasoned technical sales professional with experience navigating large, complex enterprise environments., • Exceptional at building relationships at the technical level and engaging confidently with enterprise architects and IT leadership., • Naturally inquisitive, you ask thoughtful, probing questions that uncover needs customers haven’t yet articulated, • Adept at managing long sales cycles and maintaining technical momentum throughout the process, • Collaborative and team-oriented, you work in perfect sync with your Client Executive and see your partnership as the foundation of success., • Highly organized, self-motivated, and comfortable balancing strategy with execution., • 7+ years of recent experience in technical sales engineering, pre-sales engineering, or solutions consulting/engineering positions., • Proven success supporting and selling to Fortune 500 or global-scale enterprise customers., • Track record of architecting and delivering multi-million-dollar deals involving complex technical solutions, • Deep technical understanding of storage technologies and the components surrounding enterprise data infrastructure. At NetApp, we embrace a hybrid working environment designed to strengthen connection, collaboration, and culture for all employees. This means that most roles will have some level of in-office and/or in-person expectations, which will be shared during the recruitment process. Equal Opportunity Employer: NetApp is firmly committed to Equal Employment Opportunity (EEO) and to compliance with all federal, state and local laws that prohibit employment discrimination based on age, race, color, gender, sexual orientation, gender identity, national origin, religion, disability or genetic information, pregnancy, protected veteran status, and any other protected classification. Why You'll Thrive at NetApp At NetApp, you won't wait for the perfect moment—you'll make it. The early planning, the extra thought, the bold idea that turns good into great: That's how our people operate and how we continue to push the boundaries of data infrastructure. NetApp is the trusted partner for organizations transforming data into opportunity. As the only enterprise-grade storage service natively embedded in Google Cloud, AWS, and Microsoft Azure, we empower customers to run everything from traditional workloads to enterprise AI with unmatched performance, resilience, and security. Our culture We celebrate mold breakers, bold thinkers, and problem solvers. We reward initiative, impact, and ownership. We provide flexibility so you can balance professional ambition with your personal life. Here, differences are not just welcomed—they drive everything we do. If you're ready to innovate, rise to the challenge, and own every moment - make your next move your best one. Apply now.

The Department: Silicon Valley Power (SVP) currently provides over 40 percent of Santa Clara’s electricity from carbon-free renewable resources. In addition to using green energy from large-scale wind, solar, geothermal and hydroelectric projects outside of the area, SVP employs innovative ways to locally produce electricity by capturing and burning methane gas from a closed city landfill and using power from solar generating systems on city-owned garages and vacant, unusable land. It is the mission of SVP to be a progressive, service-oriented utility, offering reliable, competitively priced services for the benefit of Santa Clara and its customers. Being competitive in the marketplace with a continuous focus on customer service, SVP can provide economic value to the City of Santa Clara and its customers while maintaining low residential rates and offering competitive rates for all customers. The Position: Under direct supervision, the Assistant Electric Utility Engineer performs a variety of entry-level professional electric utility engineering field and office work in Electric system planning, electric system design, construction and/or maintenance programs. SVP invites applications from dynamic and innovative qualified candidates for an entry level engineering position. Assistant Electric utility engineer will be part engineering team to conduct design, establish standards and implement construction projects. Incumbents may be assigned to work in any division in the Electric Department reporting to a Principal, Senior Electric Utility Engineer, Electric Utility Engineer Division Manager, Assistant Director or Director. This recruitment may be used to fill multiple positions in this, or other divisions/departments, if a vacant position becomes available. If you're interested in employment in this classification, you should apply to ensure you are considered for additional opportunities that may utilize the applicants from this recruitment. Additional Information: Applications must be filled out completely (e.g. do not write “see resume, NA, or personnel file.”). To receive consideration for the screening process, candidates must submit a 1) Cover Letter and 2) Resume. Incomplete applications will not be considered. Application packets may be submitted online through the “Apply Now” feature on the job announcement at . This position is open until filled: Applications will be reviewed on a bi-weekly basis for consideration to the position. If you are interested in applying you are encouraged to apply as soon as possible, before the position is closed. THIS RECRUITMENT MAY BE USED TO FILL MULTIPLE POSITIONS IN THIS, OR OTHER DIVISIONS OR DEPARTMENTS BESIDES THE POSITIONS LISTED ABOVE. IF YOU ARE INTERESTED IN EMPLOYMENT IN THIS CLASSIFICATION, YOU SHOULD APPLY TO ENSURE YOU ARE CONSIDERED FOR ADDITIONAL OPPORTUNITIES THAT MAY UTILIZE THE APPLICANTS FROM THIS RECRUITMENT.MEETING THE MINIMUM QUALIFICATIONS DOES NOT GUARANTEE ADMITTANCE INTO THE EXAMINATION PROCESS. ONLY THE MOST QUALIFIED CANDIDATES WHO DEMONSTRATE THE BEST COMBINATION OF QUALIFICATIONS IN RELATION TO THE REQUIREMENTS AND DUTIES OF THE POSITION WILL BE INVITED TO TEST OR INTERVIEW. The salary range for this position is $145,678.08 – $185,797.44. This position may be filled at or near the minimum of the salary range. EDUCATION AND EXPERIENCE Minimum Education/Experience Requirements: • Graduation from an accredited college or university with:, • A Bachelor's Degree in Electrical, Mechanical or Civil Engineering from a college or university that is accredited by the Accreditation Board of Engineering and Technology (ABET). OR * None License/Certifications: Possession of a valid California Class C driver's license is required at time of appointment and for the duration of employment. Desirable Qualifications: • Registration as an Electrical, Mechanical or Civil Engineer in the State of California., • Experience using ESRI based Geographic Information System (GIS). Other Requirements: • Must be able to perform all of the essential functions of the job assignment., • May be required to work shifts, weekends, and odd and unusual hours in the performance of duties and emergency situations. Follow this link to view the entire Class Specification, which includes more information on Typical Duties and Knowledge, Skills, and Abilities. Candidates must attain a passing score on each phase of the examination process to qualify for the Eligible List. A department interview may be required prior to appointment. Federal law requires all employees to provide verification of their eligibility to work in this country. Please be informed that the City of Santa Clara will not sponsor, represent, or sign documents related to visa applications/transfers for H1B or any other type of visa which requires an employer application. VETERAN’S PREFERENCE POINTS: This position qualifies for Veteran’s Preference Points. Applicants who have separated from service (Active Duty Status) must submit proof of honorable discharge (Form DD214) with their application at time of filing or will be ineligible to have points added to their final score. The City of Santa Clara is an equal opportunity employer. Applicants for all job openings will be considered without regard to age, race, color, religion, sex, national origin, sexual orientation, disability, veteran status or any other consideration made unlawful under any federal, state or local laws. The City of Santa Clara is committed to offering reasonable accommodations to job applicants with disabilities. If you need assistance or an accommodation due to a disability, please contact us at (408) 615-2080 or . Compensation details: 145678.08-185797.44 Yearly Salary PIba85c1fca743-25405-39568110

At Johnson & Johnson, we believe health is everything. Our strength in healthcare innovation empowers us to build a world where complex diseases are prevented, treated, and cured, where treatments are smarter and less invasive, and solutions are personal. Through our expertise in Innovative Medicine and MedTech, we are uniquely positioned to innovate across the full spectrum of healthcare solutions today to deliver the breakthroughs of tomorrow, and profoundly impact health for humanity. Learn more at jnj.com As guided by Our Credo, Johnson & Johnson is responsible to our employees who work with us throughout the world. We provide an inclusive work environment where each person is considered as an individual. At Johnson & Johnson, we respect the diversity and dignity of our employees and recognize their merit. Job Function: R&D Product Development Job Sub Function: Robotics Job Category: Scientific/Technology All Job Posting Locations: Santa Clara, California, United States of America Job Description: About MedTech Fueled by innovation at the intersection of biology and technology, we're developing the next generation of smarter, less invasive, more personalized treatments. Your unique talents will help patients on their journey to wellness. Learn more at We are searching for the best talent for Senior Machine Learning Engineer, Robotics to be located in Santa Clara, CA Johnson & Johnson MedTech is inventing the future of robotic surgery with OTTAVA. This next-generation soft-tissue surgical robot will leverage advancements in AI/ML, connect health data inside and beyond the operating room, and deliver clinical innovations for patients and care teams. Purpose: We are looking for a highly skilled and innovative Senior Machine Learning Engineer to apply the latest advances in learning-based manipulation to improve the performance and safety of surgical robotics. In this hands-on role you will rapidly design models, implement algorithms, and bring ML-trained manipulation behaviors from research to real-world robotic hardware in unstructured environments. As a senior member of the team, you will be responsible for mentoring engineers and elevating the team's overall technical capabilities. You will be responsible for: • Develop and implement ML algorithms for surgical robotic manipulation\n, • Build pipelines for data collection, training, testing and deployment of ML models\n, • Leverage simulation for prototyping, training, and transfer to robot hardware\n, • Define and evaluate performance metrics for surgical tasks and implement rigorous testing protocols\n, • Collaborate with software and controls teams to deploy learned policies and ensure safe and reliable execution\n, • Optimize models for onboard real-time performance on robotic hardware\n, • Stay current with the latest robotics and AI research, mentor team members, and drive innovation\n Qualifications / Requirements: • PhD/MS in Machine Learning, Computer Science, Robotics, or related field and 0+/3+ years of work experience\n, • 3+ years of hands-on experience implementing and deploying ML models for robotic manipulation and experience with large multimodal ML models\n, • Mastery of Python for prototyping and C++ for performant, deployable code\n, • Strong proficiency in deep learning frameworks (e.g., PyTorch, TensorFlow)\n, • Strong experience with simulation platforms (e.g., MuJoCo, Isaac Sim, PyBullet) and sim-to-real transfer\n\n, • Understanding of robot kinematics, dynamics, sensing, and control\n, • Ability to travel up to 5%, domestic and international is required\n\n Johnson & Johnson is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, age, national origin, disability, protected veteran status or other characteristics protected by federal, state or local law. We actively seek qualified candidates who are protected veterans and individuals with disabilities as defined under VEVRAA and Section 503 of the Rehabilitation Act. Johnson & Johnson is committed to providing an interview process that is inclusive of our applicants' needs. If you are an individual with a disability and would like to request an accommodation, external applicants please contact us via , internal employees contact AskGS to be directed to your accommodation resource. #JNJDataScience #JNJMedTech-DS #LI-Hybrid Required Skills: Machine Learning Algorithms, Robotic Control Preferred Skills: Computer Programming, Cost-Benefit Analysis (CBA), Critical Thinking, Data Science, Industrial Robotics, Industry Analysis, Innovation, Manufacturing Technologies, Problem Solving, Process Improvements, Prototyping, Relationship Building, Research and Development, Robotic Automation, Robotic Control Software, SAP Product Lifecycle Management, Technical Credibility, Technologically Savvy The anticipated base pay range for this position is : The anticipated base pay rang for this position is $125,000 to $201,250 USD. Additional Description for Pay Transparency: Subject to the terms of their respective plans, employees and/or eligible dependents are eligible to participate in the following Company sponsored employee benefit programs: medical, dental, vision, life insurance, short- and long-term disability, business accident insurance, and group legal insurance. Subject to the terms of their respective plans, employees are eligible to participate in the Company's consolidated retirement plan (pension) and savings plan (401(k)). This position is eligible to participate in the Company's long-term incentive program. Subject to the terms of their respective policies and date of hire, Employees are eligible for the following time off benefits: Vacation -120 hours per calendar year Sick time - 40 hours per calendar year; for employees who reside in the State of Washington -56 hours per calendar year Holiday pay, including Floating Holidays -13 days per calendar year Work, Personal and Family Time - up to 40 hours per calendar year Parental Leave - 480 hours within one year of the birth/adoption/foster care of a child Condolence Leave - 30 days for an immediate family member: 5 days for an extended family member Caregiver Leave - 10 days Volunteer Leave - 4 days Military Spouse Time-Off - 80 hours Additional information can be found through the link below.

seeking a ML Ops Engineer to drive the full lifecycle of machine learning solutions. Predictive Al team Key Responsibilities Develop and maintain ML pipelines using tools like MLflow. Kubeflow, or Vertex Al Automate model training, testing, deployment, and monitoring in cloud environments (e.g., GCP, AWS, Azure) Implement CI/CD workflows for model lifecycle management, including versioning, monitoring, and retraining. Monitor model performance using observability tools and ensure compliance with model governance frameworks (MRM, documentation, explainability) Collaborate with engineering teams to provision containerized environments and support model scoring via low-latency APIs Leverage AutoML tools (e.g., Vertex Al AutoML, H2O Driverless Al) for low-code/no-code model development, documentation automation, and rapid deployment Qualifications 10+ Years of professional experience in Software Engineering & 3+ Years in AIML. Machine Learning Model Operations. Strong proficiency in Java and Python, SQL, and ML libraries (e.g., scikit-learn, XGBoost, TensorFlow, PyTorch). Experience with cloud platforms and containerization (Docker. Kubernetes) Familiarity with data engineering tools (e.g., Airflow, Spark) and ML Ops frameworks. . Solid understanding of software engineering principles and-DevOps practices. . Ability to communicate complex technical concepts to non-technical stakeholders.

A high-growth AI hardware company is hiring RTL Design Engineers to help develop next-generation compute platforms for large-scale machine learning workloads. The team is building vertically integrated silicon and system solutions designed to power advanced AI training and inference with exceptional efficiency and performance. This is an opportunity to work across architecture and RTL, delivering complex SoC designs that sit at the core of modern AI infrastructure. What You’ll Do: • Contribute to scalable architecture-to-RTL methodologies spanning block, subsystem, and full-chip design, • Own subsystem and/or chip-level deliverables from microarchitecture definition through sign-off-ready RTL, • Drive design reviews and milestone tracking, including progress toward area and timing closure, design freeze, and tapeout, • Partner closely with Verification, DFT, and Physical Design teams to achieve best-in-class Performance, Power, and Area (PPA), • Support structured handoff and collaboration across downstream siliconization flows What We’re Looking For: • Proven concept-to-production experience delivering ASIC/SoC subsystems or top-level designs from architectural specification through silicon, • Strong hands-on experience with SystemVerilog, Python, C/C++, Bluespec, or similar languages used in chip development, • Demonstrated experience designing high-performance compute architectures (CPUs, GPUs, accelerators), high-speed connectivity, memory management, and related subsystems, • Experience validating your own designs and partnering with verification teams to achieve performance targets and coverage closure, • Hands-on experience with synthesis, equivalence checking, linting, clock-domain crossing analysis, and related sign-off flows, • Working knowledge of DFT and physical design methodologies to enable high test coverage and optimized timing, power, and area Nice to Have: • Familiarity with verification and emulation platforms and methodologies, • Experience participating in silicon bring-up and post-silicon debug, • Hands-on experience implementing silicon and firmware-based hardware security features such as Root of Trust (RoT), secure boot, lifecycle state machines, key management, TRNG interfaces, secure debug, secure firmware updates, access control, and memory protection This role is ideal for engineers who want deep ownership of complex SoC design and to directly contribute to the silicon enabling the next wave of AI systems.

Must haves: • Electrical design exp, • AutoCAD electrical, • HV or medium voltage or Low voltage exp, • One-line diagrams Electrical Engineer, Test Setup Commissioning & Sustaining Job Category: Energy – Solar & Storage What to Expect Tesla Energy’s Systems Engineering team is looking for an Electrical Engineer to own commissioning, maintenance, debug, and troubleshooting of automated test setups. You’ll be the technical lead responsible for maintaining setup uptime—ensuring networking, controls, power distribution, instrumentation, and automation hardware operate reliably across multiple sites. You’ll own the full setup lifecycle – from electrical bring-up and network configuration to root-cause debugging and the development of Python tools to drive reliability, system visibility, and uptime. What You’ll Do • Commission & Bring-Up: Lead electrical bring-up, controls integration, network configuration, and sensor validation for new and existing test setups., • Troubleshoot & Root-Cause: Diagnose electrical, firmware, and network failures across PLCs, DAQ systems, DC power supplies, chillers/thermal controllers, and automation hardware., • Networking: Configure and maintain managed switches, VLANs/subnets, static IP maps, and controller-to-server communication; resolve connectivity issues across the test environment., • Python: Build and maintain Python scripts for automated diagnostics, health monitoring, log parsing, and rapid debugging., • Configuration Control: Maintain consistent firmware versions, IP tables, wiring standards, and hardware configurations across multiple setups., • Sustaining Engineering: Perform preventative audits, execute hardware upgrades, and retrofit engineering changes into deployed systems., • Cross-Functional Debug: Collaborate with Test Automation, Controls, Systems Engineering, and Mechanical teams to resolve integration blockers., • Documentation: Maintain detailed system configurations, track known issues, and document setup-specific quirks to prevent repeated failures. What You’ll Bring • BS in Electrical Engineering or equivalent experience, • Strong troubleshooting skills across wide range of voltage systems (3–480 V AC/DC), analog/digital signals, relay logic, sensors, and grounding, • Proficiency in networking fundamentals: TCP/IP, managed switches, VLANs, static IP assignment, • Solid Python skills for scripting/debugging and interacting with hardware APIs/libraries, • Experience with PLCs, DAQ systems (NI), and industrial communication protocols (Modbus, CAN, etc.), • Comfortable working in Linux environments (SSH, service management, network configuration), • Hands-on lab experience: cable/wire routing, component swaps, using multimeters/scopes for signal validation, • Ownership mindset: clean wiring, labeled hardware, consistent processes, well-maintained lab spaces Preferred • Experience in Lab Operations, Test Engineering, or NPI environments, • Familiarity with SCADA systems or containerized tooling (Docker), • Exposure to high-voltage safety and power electronics environments

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. About The RoleAs a lead front-end design engineer, you will be a key part of the world-class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE). This role requires deep expertise in RTL design and integration, with a strong focus on delivering high-performance, power-efficient, and scalable solutions. The role also requires close collaboration and management of external ASIC vendor. You will collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of building WSE systems. Responsibilities • Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis., • Managing external ASIC vendor through product development cycle., • Work closely with PD team members for design closure to meet PPA goals., • Work closely with Design verification and DFT teams for achieving the best functional and test coverage., • Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product., • Debug silicon-level functional, timing, and power issues during bring up.Requirements, • Master’s degree in Computer Science, Electrical Engineering, or equivalent., • Can work in a hybrid work environment., • 8-15 years of experience in delivering complex, high performance high quality RTL designs., • Experience with Front End Chip integration and third-party IP integration., • Demonstrated experience in networking, high-performance computing, machine learning or related fields., • Proven track record of multiple silicon success., • Experience collaborating and managing external vendors., • Experience with designing/integrating high speed IO., • Networking stack experience including TCP/IP, RDMA and Ethernet., • Knowledge of PCIe, CPU interfaces and Serdes technology., • Working knowledge of scripting tools : Python, TCL.Assets This offer is contingent upon Cerebras successfully obtaining an export license from the U.S. Department of Commerce’s Bureau of Industry and Security authorizing the release to you of certain software source code and/or technology that is subject to the Export Administration Regulations. However, we can make no assurances with respect to the final disposition of an export license application. Why Join Cerebras People who are serious about software make their own hardware. At Cerebras we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we’ve reached an inflection point in our business. Members of our team tell us there are five main reasons they joined Cerebras: • Build a breakthrough AI platform beyond the constraints of the GPU., • Publish and open source their cutting-edge AI research., • Work on one of the fastest AI supercomputers in the world., • Enjoy job stability with startup vitality. This website or its third-party tools process personal data. For more details, click here to review our CCPA disclosure notice.

HCLTech is looking for a highly talented and self- motivated Principal AI Architect to join it in advancing the technological world through innovation and creativity Title: AI Architect Location Santa Clara (USA) As an AI Architect, you will guide the strategy and delivery for interoperable, compliant, and economically viable modern AI solutions. You will architectures across a Hybrid AI landscape, blending Frontier Models (Azure OpenAI/Gemini) with Cost-Efficient Small Language Models (SLMs) and Edge Inference. You will craft solutions based on advanced AI technologies from OpenAI, NVIDIA, Google, , Microsoft and AWS. This role has a focus on enabling advanced Agentic AI solutions that transform core business functions and enable the future hybrid workforce. Working at the highest levels, you will engage AI, Technology and Business leaders in the world’s most successful organizations. You will lead architectural design, establish best practices, for our most complex AI initiatives. This role requires a combination of deep hands-on technical expertise in advanced AI with strategic business acumen, serving as both a technical authority and a trusted advisor to clients Key Responsibilities What you’ll do Multi-Agent Architecture Patterns: Define and govern reference architecture for multi-agent systems, covering hierarchical, peer-to-peer, and sequential (ReAct) orchestration models. Guide teams on pattern selection based on client use cases. Memory System Design: Architect the standards for integrated memory systems, including short-term session state, long-term knowledge via vector databases and knowledge graphs, and episodic/audit memory. Ensure coherent retrieval strategies across layers. Retrieval-Augmented Generation (RAG) and CAG (Cache Augmented) Architecture: Define architectural patterns for end-to-end RAG pipelines, including chunking, embedding, vector search (e.g., Azure Cognitive Search, pgvector), and reranking. Ensure designs include standards for lineage, observability, and evaluation (e.g., RAGAS). Cross-Cloud & Vendor Integration: Create and maintain decision frameworks for platform selection (e.g., Copilot Studio for Teams integration, Vertex AI for GCP workloads). Advise clients on balancing vendor lock-in risks with integration benefits. GenAIOps & Observability: Define the architectural standards for GenAIOps, including CI/CD, IaC, and observability. Establish standard metrics to track agent decision traces, latency, token consumption, hallucination, and cost. Safety, Security & Governance: Architect enterprise-wide guardrails for safety (hallucination mitigation), security (prompt injection defense, PII masking), and fairness (bias detection). Apply governance frameworks (NIST AI RMF, ISO 42001) and design human-in-the-loop (HITL) workflows. Enterprise Integration & Scalability: Architect scalable integration patterns for agentic systems with enterprise platforms (Microsoft Entra ID, Teams, Dynamics/Salesforce, ERPs) and compute (Kubernetes). Ensure patterns address security, data residency, and compliance. Technical Leadership & Client Advisory: Combine technical architecture with strategic guidance. Lead C-level workshops on Agentic AI adoption, advise on roadmaps, and shape technology strategy. Mentor other architects and contribute to industry thought leadership. Thought leadership and public speaking: Present at industry events and publish articles that advance the AI industry. Core Qualifications (The Bar) -Enterprise Experience: 8–10+ years in technical leadership, with a strong background in both software engineering and enterprise-scale cloud architecture. -Cloud Expertise: Architectural expertise with one primary cloud platform (Azure, GCP, or AWS) and hands-on familiarity with at least one other. -GenAI & LLM Depth: Demonstrated experience architecting and guiding solutions using GenAI platforms (e.g., Azure OpenAI, Vertex AI, or AWS Bedrock). -RAG & Orchestration: Proven experience designing complex RAG pipelines. -Model Fine-tuning: Experience with instruction tuning or fine-tuning strategies for LLMs. -Leadership & Advisory Skills: Exceptional communication skills with demonstrated experience advising senior stakeholders (Director/C-Level) on technical strategy, roadmaps, and governance Desired Skills & Experience • Multi-Agent Systems: Deep understanding of, and experience designing or prototyping, advanced multi-agent systems (e.g., task decomposition, collaborative agents)., • Multi-Cloud Experience: hands-on architectural expertise across all three major clouds (Azure, AWS, GCP)., • GenAI Ops & Governance: Hands-on experience with GenAI Ops tooling. Familiarity with AI governance frameworks (NIST AI RMF, ISO 42001) and their practical application. And AI FinOps & Model Routing, • Framework Expertise: Hands-on development experience with one or more orchestration frameworks (e.g., LangChain, LlamaIndex, Semantic Kernel)., • Thought Leadership & Open Source: Published work (whitepapers, patents), conference speaking engagements, or active contributions to relevant open-source projects. HCLTech offers a highly competitive compensation package for this role, commensurate with experience. This includes a base salary, performance-based bonus, and comprehensive benefits. A specific salary band will be discussed with qualified candidates during the initial screening process. Scope by Level Senior Architect: Own end-to-end architecture for 1–3 programs/accounts. Lead technical architecture reviews and decision-making on agentic design patterns. Mentor senior engineers and emerging Architects. Drive thought leadership through internal documentation and architecture governance. Represent HCLTech in client C-level conversations for assigned accounts. Principal Architect: Portfolio-level ownership across multiple clients and programs. Define enterprise strategy for agentic AI adoption—roadmaps, best practices, architectural standards, and governance frameworks. Influence global partner strategies (Microsoft, Google, AWS) and contribute to HCLTech’ s overall AI/Cloud roadmap. Represent HCLTech as a recognized industry leader through conference speaking, published research, and advisory board participation. Mentor other architects and shape hiring/capability building for the AI architecture practice. Soft Skills & Behavioural Competencies We are looking for professionals who combine deep technical expertise with strong interpersonal and leadership abilities. Specifically: • Clear, Multi-Level Communication, • Strategic Thinking & Advisory Mindset, • Cross-Functional & Cross-Vendor Collaboration, • Pragmatic Problem-Solving, • Ownership & Accountability, • Continuous Learning & Adaptability, • Customer Obsession & Trust-Building, • Leadership & Mentorship, • Change Agent Mindset Pay and Benefits Pay Range Minimum: Base $ 200000 Per Year Pay Range Maximum: Base $ 220000 Per Year HCLTech is an equal opportunity employer, committed to providing equal employment opportunities to all applicants and employees regardless of race, religion, sex, color, age, national origin, pregnancy, sexual orientation, physical disability or genetic information, military or veteran status, or any other protected classification, in accordance with federal, state, and/or local law. Should any applicant have concerns about discrimination in the hiring process, they should provide a detailed report of those concerns to for investigation. A candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year); and 10 paid holidays per year How You’ll Grow At HCLTech, we offer continuous opportunities for you to find your spark and grow with us. We want you to be happy and satisfied with your role and to really learn what type of work sparks your brilliance the best. Throughout your time with us, we offer transparent communication with senior-level employees, learning and career development programs at every level, and opportunities to experiment in different roles or even pivot industries. We believe that you should be in control of your career with unlimited opportunities to find the role that fits you best.

Senior Laser Design Engineer Overview We are seeking a Senior Laser Design Engineer to play a key role in the design and development of semiconductor laser products for high-volume manufacturing. This position involves close collaboration with internal cross-functional teams and external manufacturing partners to deliver high-performance, reliable laser devices. Key Responsibilities • Design and develop epitaxial structures for semiconductor laser diodes, including DFB and related architectures, to optimize performance metrics such as optical power, efficiency, wavelength stability, beam quality, modulation speed, and reliability, • Analyze experimental and manufacturing data to establish correlations between device performance and design parameters, • Perform failure analysis and root-cause investigations related to device functionality, yield, and long-term reliability, • Collaborate closely with epitaxial growth, device integration, process, packaging, and test teams throughout the product development lifecycle, • Support the transition of designs from development to volume manufacturing, • Interface with external foundries and partners as needed, • Occasional, limited travel may be required Qualifications • Ph.D. in Electrical Engineering, Materials Science, Physics, Optics, or a related field, • Minimum of 1-4 years of industry experience in semiconductor laser development, • Hands-on design experience with DFB or other laser diode architectures, • Experience with GaAs- or InP-based laser devices is a plus, • Familiarity with wafer processing, epitaxial characterization, packaging and testing, reliability testing, and failure analysis, • Strong understanding of laser diode physics, modeling, and device behavior, • Demonstrated track record of successful laser diode development, • Self-motivated, detail-oriented, and effective collaborator in a cross-functional environment

Position Overview The Staff Manufacturing Engineer supports contract manufacturers and suppliers in launching, scaling, and improving manufacturing processes for products. This role leads process validation, equipment development, cost improvement, and continuous improvement initiatives to ensure high-quality, efficient, and compliant production. Key Responsibilities • Serve as the primary technical contact for contract manufacturers and suppliers, • Lead manufacturing process transfer from R&D to production, • Support supplier selection, qualification, and capacity planning, • Develop and execute process validations and documentation (IQ/OQ/PQ, PFMEA), • Drive process improvements, yield improvement, and cost reduction projects, • Implement lean manufacturing tools (6S, Kanban, JIT, visual management), • Support design for manufacturability (DFM) during product development, • Develop manufacturing equipment, tooling, fixtures, and work instructions, • Lead new product introductions and design transfer to production, • Investigate product and process issues and implement corrective actions, • Ensure compliance with FDA, ISO, and quality system requirements, • Bachelor’s degree in Mechanical Engineering or related field (Master’s preferred), • 8+ years of manufacturing/process engineering experience (6+ with Master’s), • Experience launching and transferring manufacturing processes, preferably in medical devices, • Strong problem-solving and statistical analysis skills (DOE, Cpk, Gage R&R), • Experience with lean manufacturing and continuous improvement, • Experience in regulated environments (FDA, ISO, cGMP), • Hands-on experience with catheter, stent, or similar device manufacturing preferred, • SolidWorks experience a plus, • Strong communication and project management skills, • Willingness to travel internationally as needed

Company Description Hadron Energy specializes in Micro Modular Reactor (MMR) development, design, and research based in the San Francisco Bay Area. As the leading MMR developer, Hadron Energy is building factory-produced, transportable microreactors that provide 24/7 carbon-free power for data centers, government facilities, industrial sites, and remote communities. Our mission is to create a brighter, healthier, and more equitable energy future. Component Design & Structural Analysis Engineer – Role Description This is a full-time on-site role for a Component Design & Structural Analysis Engineer, based in the San Francisco Bay Area, New York City, or remote. This position is ideal for candidates with strong mechanical design, structural modeling, and analysis experience who are passionate about developing advanced, safety-critical components for next-generation nuclear systems. The Component Design & Structural Analysis Engineer will be responsible for the detailed mechanical design and structural evaluation of reactor components, subsystems, and support structures within Hadron Energy’s micro modular reactor (MMR). This individual will work closely with reactor design, materials, thermal-hydraulics, manufacturing, and licensing teams to ensure components meet stringent functional, safety, and regulatory requirements. You will play a central role in transforming conceptual designs into manufacturable, high-performance components by using advanced simulation tools, design methodologies, and structural engineering thinking to advance Hadron’s reactor design toward commercial deployment. Responsibilities • Lead the mechanical design, modeling, and drafting of reactor components, assemblies, and supporting structures, • Perform structural, thermal-mechanical, and vibration analyses using finite element analysis (FEA) tools (ANSYS, Abaqus, COMSOL, or equivalent), • Evaluate component performance under normal operation, transient conditions, accident scenarios, seismic events, and extreme loading conditions, • Develop and maintain engineering drawings, design specifications, and technical documentation in accordance with ASME Section III and related codes, • Collaborate with thermal-hydraulics, materials, and safety engineers to incorporate multi-disciplinary requirements into component design, • Support component verification and validation testing, including prototyping, mechanical tests, and qualification activities, • Conduct design optimization studies focused on manufacturability, reliability, and cost-effectiveness, • Coordinate with manufacturing, procurement, and quality teams to ensure components meet fabrication, inspection, and regulatory requirements, • Prepare technical reports, analysis summaries, and documentation for internal design reviews and NRC licensing submittals, • Participate in hazard analyses, design reviews, and risk mitigation activities, • Stay current on best practices in structural analysis, advanced materials, and nuclear system design Qualifications & Skillsets • Bachelor’s, Master’s, or PhD in Mechanical Engineering, Structural Engineering, Nuclear Engineering, or a related discipline, • 5+ years of experience in mechanical design and structural analysis, preferably in nuclear, aerospace, defense, or high-reliability industries, • Proficiency with FEA tools such as ANSYS, Abaqus, COMSOL, or equivalent, • Strong understanding of ASME Section III, pressure boundary design, materials behavior, and structural mechanics, • Experience evaluating components under thermal, seismic, and dynamic loads, • Familiarity with CAD software (SolidWorks, CATIA, Inventor, or similar) and PDM/PLM systems, • Knowledge of materials, welding, fabrication processes, and component qualification practices, • Excellent analytical, technical writing, and communication skills, • Ability to work collaboratively across multidisciplinary engineering teams, • High attention to detail, rigorous documentation practices, and commitment to engineering excellence, • Passion for clean energy, advanced technology, and designing components that enable safe, scalable nuclear power

Qualifications: • B.S. in Mechatronics, Mechanical Engineering, Electrical Engineering, or Robotics, • 2–5 years of professional experience in product design, robotics, or industrial automation, • Strong proficiency in parametric 3D modeling, • Experience carrying a PCB design from schematic to manufacturing, • PLC programming and industrial communication protocols (Modbus, EtherCAT, or CAN), • Proficiency with lab equipment (oscilloscopes, multimeters) and shop tools (soldering, basic machining), • Experience with 480 3ph and large battery systems, • Experience programming microcontrollers (C/C++) or Python scripting desired, • Familiarity with ROS is helpful, • Design mechanical mechanisms, enclosures, and robotic end-effectors, • Create detailed manufacturing drawings (GD&T), bills of materials (BOMs), and assembly instructions, • Size and select electro-mechanical components such as motors, • Design and build test fixtures to validate mechanical life and reliability, • Design and layout mixed-signal PCBs for sensor interfacing, power management, and motor control, • Manage the PCBA fabrication process, • Design industrial cable harnesses and manage interconnects

The Catholic Institute of Technology invites applications for a tenure-track position at the rank of Assistant/Associate Professor in the Department of Mechanical Engineering. We are seeking a highly qualified candidate with a Ph.D. in Mechanical Engineering or a closely related field, who has a proven track record of high-quality publications in high-impact journals and significant academic contributions. This position is in-person at our campus in Castel Gandolfo, Italy. This position is based full-time in Castel Gandolfo, Italy, with active recruitment in the Bay Area, consistent with our mission as an American technical university. Depending on the role and institutional needs, arrangements may be negotiated to allow for time split between Castel Gandolfo and the Bay Area to support networking, research collaborations, and strategic partnerships. About the Catholic Institute of Technology We are a Catholic research university whose mission is to integrate the wisdom of revelation with the truths that are discoverable to human reason. Located in the scenic Alban Hills of Castel Gandolfo, CatholicTech is a leading institution for scientific research and technical education. Steeped in the Catholic Tradition, and formed by the rich liturgical, academic, and social life, our students are taught to see beauty and seek knowledge of the truths that are revealed in the splendor of creation. To that end, we provide them with a rigorous education in philosophy, theology, and the sciences, along with the tools for advanced research and innovation. We are firm believers in the hands-on approach to the learning of science and engineering, as it fosters curiosity and deepens understanding. By actively engaging students in problem-solving, research, and real-world engineering projects, we bridge the gap between theory and practical problem-solving, empowering students to become confident and competent practitioners. We aspire to be a community of saints, scholars, and scientists who are equipped to serve the Church and society through research and work that is informed by faith, reason, and virtue. Responsibilities: • Conducting innovative and impactful research in the field of Mechanical Engineering., • Publishing research findings in high-impact, peer-reviewed journals., • Teaching undergraduate and graduate courses in Mechanical Engineering and other related subjects., • Mentoring and advising students., • Contributing to the academic community through service and leadership roles. Qualifications: • Ph.D. in Mechanical Engineering or a closely related field., • At least 3 years of academic experience post-Ph.D., • Strong record of high-profile publications in high-impact journals., • Demonstrated excellence in teaching and mentoring., • Commitment to fostering an inclusive and dynamic academic environment. Compensation: Compensation will be commensurate with qualifications and experience and will be competitive within academia. Application: candidates should submit the following: • A cover letter detailing their research and teaching experience., • Curriculum vitae, • Copies of key publications, • A statement of research interests and future plans, • Contact information for three professional references Contact Information:

Job Title: PLM System Design Engineer Location: Sunnyvale Remote Duration: Long Term Client: Wipro Job Description Customer is looking for a candidate with strong business strategy and planning skills who can lead discussions with business stake holders to sell value of a proposed technical initiative. He should be able to create presentations for leadership and for business meetings to articulate the vision for the technical project. So, I think strong business communication skills and experience of project strategy, planning and roadmap etc. are key requirements. Minimum Qualifications • Bachelor’s degree in industrial engineering, or related field (Manufacturing, Mechanical, Electrical, etc.), • 5-7+ years of experience of leading global supply chain initiatives improving processes in the electronics industry - design, sourcing, manufacturing, logistics, fulfillment, after-sale service, • Deep PLM and Operations / Supply Chain process experience and be self-directed, motivated, and comfortable working in an extremely fast-paced environment, • Technical proficiency in PLM enterprise software, integration technologies, and data platforms, • Extensive experience in global supply chain management specific to New Product Introduction (NPI) at a global scale, • Comprehensive knowledge of how PLM data is used across enterprise, manufacturing, and supply chain processes. Ability to identify uses cases where improved data will bring significant benefit to teams, mobilize POC’s, and scale rapid solutions., • Hands on experience working with PLM data across the enterprise translating how data enables business processes and recommends process Efficiency improvements resulting from data processing improvements and realize the benefit, • Strong analytical, project management and leadership skills to handle a variety of activities and complexities spanning the organization and be willing to work at both a very detailed and strategic level, • The ability to facilitate global projects and to align business and technical teams, • Exceptional communication skills, verbal, written and presentation to easily communicate complex technical concepts to executive leadership, • Solid ability to personally deliver large scale global initiatives under pressure, with high levels of complexity and ambiguity, • Identify build strong business cases for the Data Foundation use cases. Assist in the mobilization of POC’s and projects to mobilize the use cases. Preferred Qualifications • Master’s degree in industrial engineering, or related field (Manufacturing, Mechanical, Electrical, etc.), • Ability to operate independently with conviction and drive teams to the right levels of quality in delivery even under pressure., • Handle ambiguity in problem definition, have a good handle on business value and have the initiative to craft problems and projects so that they deliver maximum impact.

Job Title: Validation Engineer Location: Mountainview, CA Role & Responsibilities • Lead end-to-end validation of Infotainment and Telematics platforms on a Linux test host machine using pytest., • Strong expertise in Python programming and the pytest framework., • Strong Linux knowledge., • Strong Git knowledge., • Perform DV testing of ICI and Telematics platforms., • Strong coordination skills with customer stakeholders and offshore teams, • Hands-on experience with automotive testing and lab equipment, including:, • Automotive Ethernet (iperf testing), • Audio analyzers, • Function generators, • MSO (Mixed Signal Oscilloscope), • Wi-Fi / Bluetooth testers, • CAN, • A2B, • RF signal generators (AM, FM & SDARS), • GNSS simulators, • 3G / 4G / 5G network simulators, • I/O protocols (I²C, GPIO, PWM, ADC), • Serial communication protocols, • Experience in EMC, thermal chamber, and vibration testing., • Experience working with Git and CI/CD pipelines., • Strong debugging skills, including issue triaging, reporting, and tracking.

Job Title: Sr. Hardware Design Engineer - Analog and Circuit design Location: Mountain View, CA Duration: Long Term Job Summary The Senior Hardware Design Engineer will be responsible for the design, development, and validation of automotive electronic hardware systems. The role requires strong expertise in analog and digital circuit design, automotive hardware development processes, and functional safety compliance per ISO 26262. The candidate will work closely with cross-functional hardware and system teams to deliver high-quality, safety-compliant automotive solutions. Key Responsibilities • Design and develop analog and digital electronic circuits for automotive applications., • Execute complete automotive hardware development activities in alignment with industry standards and internal processes., • Perform hardware safety analyses, including:, • Worst Case Circuit Analysis (WCCA), • Design Failure Mode and Effects Analysis (DFMEA), • Failure Modes, Effects, and Diagnostic Analysis (FMEDA), • Fault Tree Analysis (FTA), • Ensure compliance with ISO 26262 Functional Safety requirements throughout the hardware development lifecycle., • Utilize engineering and analysis tools such as Mathcad, Ansys Medini, and other relevant software tools., • Collaborate closely with hardware, systems, and cross-functional teams through continuous and effective communication., • Bachelor’s or Master’s degree in Electrical, Electronics, or related Engineering discipline., • 5–10 years of experience in hardware design for automotive applications., • Strong hands-on experience in analog and digital circuit design., • In-depth knowledge of automotive hardware development processes and standards., • Proven experience working with ISO 26262 Functional Safety standards., • Hands-on experience performing WCCA, DFMEA, FMEDA, and FTA., • Proficiency with engineering tools such as Mathcad, Ansys Medini, or equivalent., • Strong communication skills and ability to work effectively in a team-oriented environment.

Job Title: Automotive Test Engineer – (Infotainment & Telematics) Location: Mountain View, CA Job Type: Full-Time Summary: Seeking an experienced Automotive Test Engineer to validate Infotainment and Telematics systems with strong test automation and IVI interface testing experience. Key Skills & Responsibilities: • Automotive test development & execution (10+ yrs), • 2+ yrs in Infotainment/Telematics testing, • Test automation for IVI interfaces, • Testing of at least two: Serialized displays, Ethernet, Wi-Fi, Bluetooth, V2X, LTE, GNSS, Audio HIL/SIL, CAN/FlexRay/Ethernet, Python/CAPL/LabVIEW, Android/QNX.

Robotics Research Engineer 📍 Palo Alto, CA (On-site) 💰 $150,000–$180,000 Base + 0.5–1% Equity 🚀 Pre-Seed Robotics Startup | General-Purpose Robotics Platform Mor Search are partnering with a well-funded, early-stage robotics company building what they describe as the “PCs of robotics” — an open, affordable, general-purpose robotic platform designed to unlock a new ecosystem of builders. They’re hiring a Robotics Research Engineer to join their founding team in Palo Alto. This is a genuine 0→1 opportunity to work across the entire stack — from cloud-based models to firmware and hardware — in a highly ambitious, deeply technical environment. What they’re looking for: • Exceptional programming fundamentals, • Evidence of independently built projects (portfolio/GitHub strongly valued), • Research background (academic or independent), • Exposure to hardware, firmware, or PCB design, • High learning velocity and strong builder mentality A formal robotics background isn’t required. Strong CS or Maths foundations plus a willingness to get hands-on with hardware is equally compelling. Package: • $150K–$180K base, • 0.5–1% equity, • Relocation support, • Health, vision & dental If you’re interested in building open robotics infrastructure from the ground up — message me directly.

iSoftStone, Inc. is seeking a SAAS Application Engineer to join our Team in Palo Alto, CA! Responsibilites: Saas Application Management: • Administer and manage a portfolio of SaaS applications, including Slack, Jira, Confluence, Miro, GSuite (Google Workspace), Notion, Zoom, and GoDaddy., • Configure and maintain user accounts, access controls, and permissions for these SaaS platforms., • Manage integrations between SaaS applications to ensure smooth workflows and data flow across platforms., • Handle SaaS vendor relationships, including managing licenses, subscriptions, renewals, and service agreements., • Ensure that applications are up-to-date with the latest features and security patches., • Administer and manage a portfolio of SaaS applications, including Slack, Jira, Confluence, Miro, GSuite (Google Workspace), Notion, Zoom, and GoDaddy., • Configure and maintain user accounts, access controls, and permissions for these SaaS platforms., • Manage integrations between SaaS applications to ensure smooth workflows and data flow across platforms., • Handle SaaS vendor relationships, including managing licenses, subscriptions, renewals, and service agreements., • Ensure that applications are up-to-date with the latest features and security patches. Automation and Integration: • Implement automation workflows using tools like Zapier, Power Automate, or platform-native automation features to streamline repetitive tasks., • Set up and manage APIs or native integrations between applications (e.g., linking Jira with Slack, Zoom, and Confluence)., • Design and optimize custom workflows for specific teams using automation tools, ensuring integration with existing systems., • Monitor the health and performance of integrations and take action to resolve any issues. Security and Compliance: • Ensure that all SaaS applications adhere to company security policies and standards., • Implement Multi-Factor Authentication (MFA), Single Sign-On (SSO), and Role-Based Access Control (RBAC) across SaaS platforms., • Work with IT and security teams to perform regular security audits, vulnerability scans, and compliance checks on SaaS platforms., • Oversee data retention, backup, and disaster recovery plans for SaaS tools. Support and Troubleshooting: • Provide Tier 2 and 3 support for issues related to the SaaS applications, resolving technical issues promptly and minimizing downtime., • Troubleshoot issues related to user access, permissions, connectivity, and application functionality., • Coordinate with SaaS vendors to resolve critical application issues or service outages., • Serve as the point of contact for end-users experiencing issues or needing guidance on SaaS tools. User Training and Documentation: • Provide training and resources to employees for effective use of the SaaS platforms, ensuring widespread adoption of best practices., • Develop and maintain documentation on configurations, processes, and troubleshooting for each SaaS application., • Conduct workshops or one-on-one training sessions to help users maximize the productivity of tools like Jira, Confluence, Slack, Miro, and Zoom. Optimization and Reporting: • Continuously monitor usage and performance metrics of SaaS applications, optimizing configurations and integrations as needed., • Work with business units to identify opportunities to enhance workflows and improve user experience with the tools., • Generate reports on application usage, performance, and costs for stakeholders, helping to manage SaaS-related budgeting and licensing. Domain and DNS Management (GoDaddy): • Administer domain names and DNS settings through GoDaddy or other domain providers., • Ensure correct configurations for email services, website hosting, and other web services linked to company domains., • Troubleshoot domain-related issues, including DNS errors, email routing problems, and SSL certificate installations. Pay Range: $38 - $42/hr iSoftStone is a global IT service and consulting company that creates value and drives success through technology solutions, service excellence, and digital innovation. We specialize in web and application development, software testing and support, data and content management, digital experience, accessibility, and data for machine learning and AI. With 20 delivery centers and more than 90,000 employees worldwide, iSoftStone is proud to serve some of the world’s most well-known businesses, including 90+ Fortune Global 500 companies. Visit us at . iSoftStone is committed to the practice of equal opportunity for all its employees and applicants in employment, and does not discriminate on the basis of race or ethnicity, color, age, national origin, religion, creed, marital status, sex, pregnancy, gender, gender identity, sexual orientation, status as an honorably discharged veteran or disabled veteran or military status, political affiliation or belief, citizenship/status as a lawfully admitted immigrant authorized to work in the United States, or presence of any physical, sensory, or mental disability. In addition, reasonable accommodation will be made for known physical or mental limitations for all otherwise qualified persons with disabilities.

ASIC Test Engineer A global research organization at the forefront of nanoelectronics and digital technology is seeking a motivated ASIC Test Engineer to join its growing Product Engineering group. The organization collaborates closely with major semiconductor foundries, IP providers, and leading technology partners to support innovation across healthcare, mobility, energy, manufacturing, and other emerging domains. Role Overview As an ASIC Test Engineer, you will serve as the primary technical interface between international customers and external test partners for integrated circuit test programs. You will oversee the full ASIC test lifecycle from prototype through volume production while ensuring technical quality, cost efficiency, and seamless customer alignment. Key Responsibilities • Define project work packages and timelines with program management, • Set up and validate ASIC test solutions with external test facilities, • Drive discussions with customers around characterization, qualification, and prototype to production ramps, • Oversee the transition into volume production and propose improvements related to yield, test efficiency, packaging options, and multi site strategies, • Conduct yield analysis and support continuous improvement initiatives during production, • Stay current with advanced packaging and next generation test methodologies through ongoing training Required Experience • Hands on experience with Teradyne UltraFLEX test systems, • Background in ASIC or semiconductor test environments, • Ability to manage technical deliverables and customer communication across multiple stakeholders, • Familiarity with high volume test processes, qualification, and production ramps preferred

Job Role: Motion Planning Autonomy Test Specialist Job Type: Full Time Location: Bay Area, CA Role Overview We are looking for a Motion Planning Autonomy Test Specialist with strong ADAS and autonomous driving experience to support vehicle-level testing and validation of motion planning features. The ideal candidate will have hands-on experience with autonomy systems, simulation environments, and vehicle testing, along with a solid understanding of vehicle dynamics and ADAS functionalities. Responsibilities ● You will develop and maintain vehicle test plans, supporting on and off site ensuring comprehensive coverage of new site enablement features. ● You will manage test scheduling and coordination, working with vehicle operations to maximize testing efficiency. ● You will perform first-pass triage of simulation and vehicle test results, identifying issues and categorizing them for engineering review and solution development. ● You will document test findings and identify opportunities to streamline processes and create reports that help autonomy engineers quickly understand test outcomes. Qualifications ● Ability and willingness to travel for test support ● Familiarity with scripting languages (Python preferred) for automation and data analysis ● Strong organizational skills with experience managing schedules or coordinating technical workflows ● Experience with simulation environments or game engines ● Exposure to robotics, automotive, or autonomous systems ● Familiarity with version control (Git) and issue tracking systems (JIRA or similar) ● Experience with test engineering, QA, or validation processes ● Understanding of basic vehicle dynamics or motion planning concepts

🚀 We’re Hiring: RTL Design Engineer 📍 Location: Bay area 🕒 Type: Full-Time 🌟 About the Role We’re looking for an RTL Designer to join our clients team! 🎯 What We’re Looking For • 12+ years of RTL Design experience, • High-Speed Protocols (Ethernet, PCIE, SerDes, UCIE), • PCS / PHY Level 🎁 What We Offer ✨ Base Salary - up to $300k ✨ Full benefits (401k, health, etc.) 📩 Apply below or reach out to me for more details!

Responsibilities • Collaborate with the marketing and sales teams to drive business expansion by identifying and addressing customer business and technical needs, providing consulting and planning services, formulating solutions, overseeing delivery and implementation, and leading pre-sales POC tests., • Create customer benchmark projects in industries such as the internet and new economy, develop replicable scenario-based solutions, improve sales efficiency, and collaborate with the marketing team for market promotion., • Continuously refine the value proposition of the company's products and solutions by analyzing the competitive dynamics of industry products, including Amazon Redshift, Snowflake, and Google BigQuery., • Stay attuned to evolving industry trends and customer needs, maintain strong collaboration with the product development team, and drive ongoing innovation and iteration of the company’s products. Qualifications • Bachelor's degree or higher, with over 5 years of experience in data warehousing and big data platforms, along with a strong understanding of big data technology stacks and data warehouse architectures., • Possess a deep understanding of industry customers' business scenarios and technology stack applications, with experience in big data consulting and implementation, enabling quick comprehension of customer needs and the ability to propose effective solutions., • Strong skills in building and maintaining customer relationships., • Excellent verbal communication and customer interaction skills, with a proactive approach to customer service and the ability to handle stress effectively. Preferred Qualifications • Familiarity with data analysis platforms such as Apache Doris, ClickHouse, Greenplum, CDH, Impala, Presto, Druid, and Kylin is preferred., • Candidates with a strong interest in technology sharing and evangelism, along with experience in public technology presentations, are highly desirable.

Title: Technical Project Manager/Senior Principal Engineer – Wireless Charging (MR / MI / Automotive) We are seeking a senior wireless charging expert to lead system architecture, technical decisions, and project execution for MR (Magnetic Resonance) and MI / Qi (Magnetic Induction) wireless charging across automotive, industrial, and consumer applications. The role requires deep hardware and firmware expertise, system-level thinking, and technical leadership to drive products from concept to mass production. Key Responsibilities System Architecture & Leadership • Lead MR / MI system architecture (Tx/Rx, power, RF, EMC, thermal, firmware), • Define system-level tradeoffs: efficiency, thermal, EMI, performance, cost, reliability, • Mentor HW/FW teams and review designs, • MR (100 kHz–MHz, long-distance, high-power) and MI (Qi/WPC) for consumer/mobile, • Resonance tuning, Q factor, coupling coefficient, coil design, L/C matching, • Inverter, DC-DC, AC-DC/DC-AC power design, • EMI/EMC mitigation, shielding, ferrite use, thermal design, • MCU architecture (ARM Cortex-M), PWM/Timer/ADC control, • Closed-loop control (power, temperature, FOD), • Qi protocol stack, inverter/DC converter control, OCP/OVP protection, • Automotive-grade system design; CCC Digital Key/NFC integration, • Standards: ISO 7637/11452, CISPR 25, ISO 26262, ISO 21434, • Software/system integration: AUTOSAR, CAN/LIN, UDS, OTA/Bootloader, • Ansys HFSS/Maxwell, COMSOL, Keysight ADS, • EMC validation, CANoe debugging & system modeling Qualifications & Requirements • Bachelor’s or Master’s degree in Electrical Engineering, Mechanical Engineering, or a related field., • 3-4 years of experience in engineering project management, with a focus on hardware implementation (preferred experience in Aerospace or Automotive industries)., • Strong technical problem-solving skills and a proven track record of addressing complex hardware challenges., • Ability to thrive in a fast-paced, dynamic environment while managing multiple stakeholders and maintaining excellent customer relations., • Willingness to travel 25%-30% for on-site installations and collaboration with engineering teams at different locations., • A hands-on mindset, with demonstrated experience in troubleshooting and hardware implementation, and the willingness to remain actively engaged in hands-on tasks. This role offers an exciting opportunity to contribute to the evolution of wireless charging technology in both automotive and consumer sectors. Join our innovative team and help drive the future of sustainable charging solutions! Foxconn Interconnect Technology, Inc. (“FIT”) focuses on the development, manufacturing and marketing of electronic and optoelectronic connectors, antennas, acoustic components, cables and modules for applications in computers, communication equipment, consumer electronics, automobiles, industrial and green energy field products. We offer our employees competitive compensation and world class benefits. In addition, we recognize the performance of the company, business unit and individual through our incentive and recognition programs. At FIT, base pay is one part of our total compensation package. Individual pay is determined by several factors including but not limited to geography, job related knowledge, skills, experience, and relevant education and/or training. FIT is an equal opportunity employer Minorities/Females/Protected Veterans/Disabled.

The ideal candidate will be responsible for assisting the project manager and project team with project documentation and control, job cost accounting, scheduling, and construction supervision efforts. In order to be successful, this candidate should feel comfortable taking on many tasks that require various skills, and appropriately prioritizing those tasks' completion. Responsibilities • Assist with on-site management to ensure project success, • Ensure project plan is moving forward to meet anticipated deadlines, • Responsible for RFI and submittal process, • Processes owner billings and project related accounting issues Qualifications • Bachelor's degree in Mechanical or Industrial Engineering or equivalent experience, • 1 - 3 years' of experience as a project coordinator, project engineer, or project manager, • Strong experience in AutoCad and Microsoft Office Suite, • Familiarity with rules, regulations, best practices and performance standards

AAC is looking for an experienced engineer with a thermal background to join its talented and growing Thermal Products team. This person will focus on thermal components and modules such as vapor chambers and heat pipes, etc. Will support development of company expertise and capabilities by driving product development, driving tool development, and building databases and workflows. They will be a show case for company expertise and a technical leader working closely with US customers and AAC China engineering/management teams. Core Responsibilities include, but are not limited to: • Develop and optimize thermal management systems and components, perform thermal analysis, and conduct simulations using software like CFD or FEA., • Design and lead thermal testing, analyze experimental results, and ensure the product meets performance requirements., • Create and maintain technical documentation, design proposals, and reports., • Lead the resolution of complex design issues and troubleshoot problems to optimize thermal performance., • Stay updated on new thermal management technologies and research. Additional Responsibilities include, but are not limited to: • Technical interface for customer team in Cupertino; present technical documents and discuss design solutions., • Identify and communicate effectively with key stakeholders including the factory engineering/manufacturing teams and our customers to share priorities and goals., • Be available as needed to assist customers and colleagues even outside of normal business hours., • Approximately 15% international travel primarily to Asia to assist with customer visits/build activities. Qualifications • B.S. Mechanical Engineering degree and 3+ years work experience in a technical setting., • Strong understanding of thermodynamics and heat transfer principles., • Experience in designing thermal systems and components., • Experience performing multi-phase thermal simulations., • Proficiency with thermal simulation software (e.g. Comsol, Fluent, Icepak) and analysis tools., • Strong root cause analysis, deductive reasoning, and FMEA skills pertaining to thermal component and systems., • Familiar with data analyses and correlation studies as it relates to part tolerances, assembly process, and product performance., • Comfortable with standard productivity and communication tools such as Microsoft Powerpoint and Excel; familiarity with MacOS desired., • Very well organized, both in the digital world and the real world., • Fluent in English speaking and writing. Comfortable in communicating with all levels of employees and management., • [Desired] Experience with advanced thermal technologies, materials, or processes., • [Desired] Experience in product development of high-volume production products/components (design and/or manufacturing emphasis), • [Desired] Experience and/or knowledge of automated assembly processes, • [Desired] Mandarin speaking and experience traveling in China., • [Desired] Experience working with factories in China., • [Desired] Enjoys working with people of diverse backgrounds and personalities.

• 8–10 years of experience in ML Engineering, AI Platform Engineering, or Cloud AI Deployment roles., • Strong proficiency in Python with experience building production-grade AI/ML services., • Proven experience deploying and supporting GenAI applications in real-world enterprise environments., • Hands-on experience with RAG systems, embeddings, vector search, and retrieval pipelines., • Experience with orchestration frameworks including LangChain, LangGraph, and LangSmith., • Strong knowledge of model serving, inference pipelines, monitoring, and observability for AI systems., • Experience working with cloud AI ecosystems (Azure AI, Azure ML, Databricks preferred)., • Familiarity with containerization and deployment tools (Docker, Kubernetes, REST APIs)., • Exposure to vector databases such as Pinecone, Weaviate, FAISS, or Azure Cognitive Search., • Experience deploying agentic AI systems with tool integrations in production., • Strong understanding of CI/CD pipelines and DevOps practices for AI platforms., • Familiarity with enterprise governance frameworks for Responsible AI.

TITLE: Engineering Data Analyst POSITION TYPE: Full Time (W2) LOCATION: Mountain View, CA ABOUT WorldLink: WorldLink is a rapidly growing information technology company at the forefront of the tech transformation. From custom software development to cloud hosting, from big data to cognitive computing, we help companies harness and leverage today’s most cutting-edge digital technologies to create value and grow. Collaborative. Respectful. Work hard Play hard. A place to dream and do. These are just a few words that describe what life is like at WorldLink. We embrace a culture of experimentation and constantly strive for improvement and learning. We take pride in our employees and their future with continued growth and career advancement. We put TEAM first. We are a competitive group that like to win. We're grounded by humility and driven by ambition. We're passionate, and we love tough problems and new challenges. You don't hear a lot of "I don't know how" or "I can't" at WorldLink. If you are passionate about what you do and having fun while doing it; tired of rigid and strict work environments and would like to work in a non-bureaucratic startup cultural environment, WorldLink may be the place for you. For more information about our craft, visit . WHO we’re looking for: We are looking for a Engineering Data Analyst who will be responsible for supporting the Core Engineering organization. In this embedded role, you will partner directly with engineering leadership to build and maintain a comprehensive engineering intelligence platform spanning delivery metrics, quality indicators, and team health analytics across global development centers in the US, Bangalore, and Warsaw. The ideal candidate combines strong technical skills (SQL, Python, Looker) with analytical rigor and clear communication. You will work across multiple data sources—including JIRA, HR systems, Git, and CI/CD pipelines—to surface actionable insights that drive operational decisions and team effectiveness. Role and Responsibilities: Engineering Metrics & Dashboards • Design, build, and maintain dashboards for sprint velocity, cycle time, release frequency, and deployment success., • Create automated reporting pipelines using Python to reduce manual data gathering., • Track and visualize bug rates, test coverage, incident response times, and technical debt trends., • Build early warning systems to identify quality issues before they impact delivery., • Develop capacity planning models and utilization dashboards., • Analyze hiring pipeline data to support workforce planning decisions., • Connect and normalize data from JIRA, HR systems (Workday), Git repositories, and CI/CD tools., • Build reliable ETL processes to ensure data freshness and accuracy., • Deliver weekly/monthly reports to engineering leadership., • Translate complex data findings into clear, actionable recommendations., • 3-5 years of experience in data analytics, business intelligence, or a related field., • Bachelors Degree or higher in an applicable field., • Proficiency in Python or R for data manipulation, analysis, and automation., • Hands-on experience with BI/visualization tools (Tableau, Power BI, or similar)., • Self-motivated individual with the ability to thrive in a team-based or independent environment., • Detail-oriented with strong organization skills., • Ability to work in a fast-paced environment., • Limited supervision and the exercise of discretion., • Strong SQL skills with experience querying complex, multi-source datasets., • Ability to work independently and manage multiple priorities., • Experience with Looker (LookML knowledge a plus)., • Experience with engineering metrics (velocity, cycle time, DORA metrics)., • Exposure to HR/people analytics (capacity planning, attrition analysis)., • Familiarity with data pipeline tools (dbt, Airflow, or similar)., • Experience working with distributed/global teams across multiple time zones., • Background in ad tech, media, or high-growth technology companies, • Available for occasional overlap calls with Bangalore (morning) and Warsaw (afternoon) teams., • Culture Fit, • Operational Excellence – Systematic approach to problem-solving; attention to detail and data accuracy., • Self-Direction – Proactively identifies gaps and opportunities without waiting to be asked., • Global Mindset – Comfortable collaborating asynchronously with distributed teams across time zones., • Clear Communication – Explains complex analysis simply; writes documentation others can follow. The physical demands described here are representative of those that must be met by contract employee to successfully perform the essential functions of this job. Reasonable accommodations may be made to enable individuals with disabilities to perform the essential functions. While performing the duties of this job, the contract employee is occasionally required to stand, clean, crawl, kneel, sit, sort, hold, squat, stoop, stand, twist the body, walk, use hands to finger, handle, or feel objects, tools or controls, reach with hands and arms, climb stairs or ladders and scaffolding, talk or hear, and lift up to 20 pounds. Specific vision abilities required by the job include ability to distinguish the nature of objects by using the eye. Operate a computer keyboard and view a video display terminal between 50% - 95% of work time, including prolonged periods of time. Requires considerable (90%+) work utilizing high visual acuity/detail, numeric/character distinction, and moderate hand/finger dexterity. Performs work under time schedules and stress which are normally periodic or cyclical, including time sensitive deadlines, intellectual challenge, some language barriers, and project management deadlines. May require working additional time beyond normal schedule and periodic travel. WHAT we’ll bring: During your interview process, our team can fill you in on all the details of our industry-competitive benefits and career development opportunities. A few highlights include: • Medical Plans, • Dental Plans, • Vision Plan, • Life & Accidental Death & Dismemberment, • Short-Term Disability, • Long-Term Disability, • Critical Illness/ Accident/ Hospital Indemnity/ Identity Theft Protection Our success begins and ends with our people. We embrace diverse perspectives and value unique human experiences. WorldLink is an Equal Employment Opportunity and Affirmative Action employer. All employment at WorldLink is decided on the basis of qualifications, merit, and business need. We endeavor to continue our footprint as a diverse organization by highlighting opportunities for all people. WorldLink considers applicants for all positions without regard to race, color, religion or belief, sex, (including pregnancy and gender identity), age, national origin, political affiliation, citizenship status, marital status, military/veteran status, genetic information, sexual orientation, gender identity, physical or mental disability or any other characteristic protected by applicable laws. People with disabilities who need assistance with any part of the application process should contact us. This job description is designed to cover the main responsibilities and duties of the role but is not designed to be a comprehensive list of all.

Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA ○ Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM ○ Debug RTL and Gate simulations and work with design engineers to verify fixes. ○ Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC. ○ Replicate silicon bugs in simulation environments and validate fixes or SW workarounds. ○ Convert verification tests to test patterns and assist Test Engineers on ATE vector bringup. ○ Evaluate latest verification methodologies and develop scripts etc. to automate verification flows.

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. About The Role As a Test Development Engineer on our manufacturing team you will be working with diagnostics, system design, manufacturing, and quality teams to develop test automation solutions for our products from PCBA to system level. You will also work closely with our contract manufacturing sites to fulfill a complete test automation solution for manufacturing test data, yield improvement, and traceability. Responsibilities • Develop and design manufacturing test automation software/scripts to test Cerebras products from PCBA to system level., • Develop and implement GUI solutions for test automation., • Work with our contract manufacturers to develop and implement a test data reporting portal for manufacturing traceability and analysis., • Sustain our current test software and infrastructure and help root cause and resolve any manufacturing test software issues or hardware defects., • Design a web interface for user to modify/edit settings from mySQL database on AWS., • Setup the various infrastructures at our manufacturing sites to support test equipment and server operation., • Interact with contract manufacturing site for all the technical issues relating to manufacturing test., • Work with diagnostics, system design, manufacturing and quality team to bring up test automation suites for the new products.Requirements, • Bachelors in computer science, electrical engineering, or other related field., • 5+ years of experience in test automation, test development or related experience., • Skilled in C/C++, Visual Studio, Python programming languages., • Good knowledge of js, MySQL, SQL, SQL Server Reporting Service., • Good knowledge of Pexpect, SSH, Telnet, RS-232, bash script., • Good knowledge of Windows, Linux, Ubuntu, Centos, VNC viewer, Console server., • Debugging skills and knowledge of debugging complex software stack.Preferred Skills, • Experience in GUI development., • Experience in Web development., • Build a breakthrough AI platform beyond the constraints of the GPU., • Publish and open source their cutting-edge AI research., • Work on one of the fastest AI supercomputers in the world., • Enjoy job stability with startup vitality. This website or its third-party tools process personal data. For more details, click here to review our CCPA disclosure notice.

Lead PIC Design Engineer Full Time Opportunity Ideally on sight in the bay area (open to be flexible for the right candidate) 400-600K first year total compensation package (depends on skillset/experience level) Job Description: Lead the development of transmitter (Tx) PIC products, including InP laser and InP modulator for short reach or intra-datacenter applications. This role offers the opportunity to work on cutting-edge technology that addresses the growing demands of data transmission in modern data centers, telecom networks, and beyond. Requirements: • Ph.D. in Electrical Engineering or Solid-State Physics and at least ten (10+) years of successful experience designing transmitter (Tx) PIC products, including InP laser and InP modulator for short reach or intra-datacenter applications, • Device physics expertise in design, simulation, and high-speed testing, • EML (electro-absorption modulator and laser) and EAM (electro-absorption modulator) design experience, • Experience with modulator/driver co-design, • Experience with signal integrity simulation and design, • 10+ layer PIC mask generation/ownership of layout, • PIC fabrication process development proficiency, • Extensive photonic device data analysis in manufacturing environment

Position: SOC Post Silicon Validation Engineer Exp: 10+ years Location: San Jose, USA. What You’ll Be Doing / Key Responsibilities: • Lead the development and execution of bring-up and silicon validation test plans for the SoC., • Perform validation of SoC peripherals including LPDDRx, PCIe, I2C, and qSPI., • Manage and oversee all phases of the validation lifecycle, from initial bring-up to production release., • Collaborate closely with cross-functional hardware and software teams to design and implement effective validation and characterization strategies., • Develop and integrate software-based test applications for stress testing and SLT screening, working with software teams to assess system performance and hardware/software interactions under diverse conditions., • BSEE/BSCE or equivalent experience, • 10+ years of SOC validation experience, • Strong understanding of digital design, circuit design and analysis, computer architecture and SOC architecture., • Knowledge of DDR training and memory system operation a plus, • Hands-on experience with silicon bring-up, debugging, and characterization of SoC-level IPs (e.g., PCIe Gen 4/5, LPDDR4/5, PLL/DLL, NOR Flash, SPI, I2C, RISC-V processors), with familiarity in memory and I/O interfaces., • Proficiency in programming/scripting (C/C++, Perl, Ruby, Python) for automation, test, • Experience with Lauterbach Debugger for RISC-V and lab equipment (oscilloscopes, BERT, power supplies, logic analyzers)., • Solid foundation in digital design, microarchitecture, timing, power, noise, control systems, and HW/SW interaction, including firmware., • scripting, and GUI development. Knowledge of signal and power integrity is a plus.

Job Title: Automotive Validation Engineer Location: Mountainview, CA Client: TATA Elxsi Role & Responsibilities • Lead end-to-end validation of Infotainment and Telematics platforms on a Linux test host machine using pytest., • Strong expertise in Python programming and the pytest framework., • Strong Linux knowledge., • Strong Git knowledge., • Perform DV testing of ICI and Telematics platforms., • Strong coordination skills with customer stakeholders and offshore teams, • Hands-on experience with automotive testing and lab equipment, including:, • Automotive Ethernet (iperf testing), • Audio analyzers, • Function generators, • MSO (Mixed Signal Oscilloscope), • Wi-Fi / Bluetooth testers, • CAN, • A2B, • RF signal generators (AM, FM & SDARS), • GNSS simulators, • 3G / 4G / 5G network simulators, • I/O protocols (I²C, GPIO, PWM, ADC), • Serial communication protocols, • Experience in EMC, thermal chamber, and vibration testing., • Experience working with Git and CI/CD pipelines., • Strong debugging skills, including issue triaging, reporting, and tracking.

Senior Test Engineer A fantastic career opportunity for an experienced Test Engineer to join a Global Technology Company company, specialising in Semiconductor Design. Here you’ll collaborate with some of the brightest minds in the industry. In this highly visible role, you’ll play a key part in defining and designing next-generation products that power the world’s most advanced systems. Responsibilities: • Driving Innovation in Test Engineering. You will lead the development of comprehensive test strategies by collaborating closely with design teams to ensure robust test coverage and product reliability. Communicate effectively across cross-functional teams, customers, and suppliers to align on quality and performance goals., • ATE Hardware Design for NPI Success. You will design advanced Automated Test Equipment (ATE) hardware—including load boards, probe cards, and interfaces—to support New Product Introduction (NPI) and accelerate time-to-market., • End-to-End Product Lifecycle Ownership. You will manage the full product lifecycle from initial design and prototyping through high-volume manufacturing and sustaining/RMA support, ensuring seamless transitions and long-term product success., • Yield & Efficiency Optimization. You will continuously improve test yield, reduce test time, and scale multi-site testing to enhance throughput and cost-efficiency in production environments. Qualifications: • B.S./M.S. in Electrical Engineering or equivalent experience, • 4+ years of Industry Experience, • Experience and in-depth knowledge of Advantest V93k required, • Experience with Test coverage and DFT (Scan/ATPG/JTAG/BIST), • Experience working with Local and offshore OSAT's, • Experience on Smartest, Redhat and GIT/SVN, • Ability to independently learn and problem solve, • Comfort with collaboration, open communication and reaching across functional borders By applying to this role you understand that we may collect your personal data and store and process it on our systems. For more information please see our Privacy Notice ().

MSR Technology Group DBA Infomatics has been an Inc 500/5000 corporation for the last 7 years in a row. We have an urgent need for V2X Research Engineer, and this is an Onsite role in Mountain View, CA. Please find the job details below. Title: V2X Research Engineer Location: Mountain View, CA Duration: Long Term Contract Pay Rate: $43 per hour on W2 with benefits Position Description: This job will include 1) Research and development of projects on Direct/Networked V2X 2) Design and development of testbeds and vehicle proof of concept (PoC) and in-field vehicle connectivity experiments. PRIMARY RESPONSIBILITIES: The primary responsibilities will include, but are not limited to: • Contribute to Direct/Networked V2X projects:, • Design and implement vehicle to network communication architectures leveraging communication infrastructure and cloud/MEC platforms, • Integrate V2X communication methods (e.g., C-V2X, cellular connectivity) for automotive safety and traffic efficiency applications, • Create publications, invention disclosures and patents, and contribute to research reports, and white papers, • Contribute to field experiments using prototype vehicles, • Analyze the network and vehicle connectivity with hardware (OBU, network analyzer) and software setup (Wireshark and other network measurement tools), • Data analysis and visualization from communication devices and vehicle sensors to monitor, predict and improve network performance for connected vehicles Requirements: QUALIFICATIONS: Master or Ph.D. candidate in Electrical engineering, Computer Science, or Telecommunication REQUIRED SKILLS: • Good understanding of cellular communication technologies such as LTE and 5G and vehicular communication technologies such as C-V2X, • Experience with wireless communications, particularly for automotive use cases, • Knowledge about applications of vehicular communication for safety, traffic efficiency and ADAS is a plus, • Networking fundamentals (TCP/IP protocols, MQTT…) and analysis tools (Wireshark), • Familiarity with AI/ML, programming (Python, C/C++, ROS) debugging and troubleshooting in Linux based hardware & software environments If you have the above skills/experience, please share your resume in confidence to: Recruiter Name: Sravan Email: EOE

We are looking for an experienced engineer to drive post-silicon structural test debug and pattern optimization for high-volume production devices. Key Responsibilities: • Own post-silicon debug of ATPG, MBIST, and Boundary Scan patterns, • Analyze silicon failures and drive corrective actions with ATE and design teams, • Regenerate, validate, and release production-ready test patterns using Siemens DFT tools, • Correlate tester data with design intent to identify coverage gaps, • Improve yield, coverage, and overall test robustness

Project Description: The Principal Engineer, RTL Design within the NPU Hardware & Software organization, is a senior individual contributor role for an engineer with deep expertise in RTL design and development for complex digital systems, including neural processing units (NPUs) or similar advanced computing architectures. This role provides expert-level technical leadership across architecture, design, implementation, and validation of critical NPU subsystems used in ADAS, autonomous driving, and in-vehicle AI applications. Responsibilities: • RTL Design & Architecture (40%), • lead the design and implementation of complex RTL blocks, modules, and subsystems using Verilog/SystemVerilog for NPU architectures., • Collaborate with system and microarchitecture architects to define and refine specifications, translating requirements into robust RTL solutions., • Drive architectural and RTL decisions to optimize performance, power efficiency, and area (PPA) for AI workloads., • Design and optimize compute engines, data paths, and memory hierarchies for high bandwidth, latency sensitive neural network processing., • Design Optimization & Performance Analysis (40%), • Own timing analysis and timing closure strategies for complex designs, identifying and resolving critical paths., • Apply advanced low power techniques, including clock gating and power aware design methodologies, to meet aggressive power targets., • Lead area optimization efforts while preserving functional correctness and performance goals., • Ensure testability by guiding and implementing design for test (DFT) strategies to support silicon validation and manufacturing readiness., • Integration, Validation & Technical Leadership (10%), • Provide technical leadership during RTL integration, working closely with verification teams on simulation, emulation, and FPGA prototyping., • Partner with software, hardware, and system teams to ensure seamless integration of the NPU into the broader vehicle compute platform., • Review designs, mentor engineers, and set best practices for RTL quality, correctness, and maintainability., • Author and review technical documentation, including design specifications, architecture reviews, and implementation guidelines., • Technology Direction & Cross Functional Influence (10%), • Influence RTL and hardware development methodologies across programs, contributing to consistency and scalability of design practices., • Evaluate emerging tools, technologies, and design approaches relevant to AI accelerators and automotive hardware platforms., • Communicate complex technical concepts clearly to both technical and nontechnical stakeholders, supporting informed decision making. Mandatory Skills Description: • Expert communicator across global, cross-cultural, and cross-functional teams., • Strong analytical, system level, and architectural thinking., • Proven ability to lead technical initiatives without direct authority., • High bar for design correctness, validation, and quality., • Collaborative mindset across hardware, software, and verification organizations., • Extensive experience in RTL design using Verilog/SystemVerilog for complex digital systems, preferably NPUs or AI accelerators., • Proficiency with EDA tools for synthesis, simulation, and timing analysis (Synopsys, Cadence, Mentor)., • Strong understanding of computer architecture, microarchitecture, and hardware/software co design., • Experience with FPGA prototyping, emulation platforms (e.g., VCS, Palladium), and HW/SW co-verification., • Scripting experience (Python, Perl) for automation and productivity., • Deep knowledge of low power design and power optimization techniques., • Demonstrated track record of delivering complex RTL designs from concept through silicon production. Salary: 140000 - 260000 USD Gross Per Year

Job Description: 1. Expertise in routing extremely complex, automotive grade harnesses with multiple branches, splices etc., 2. Very strong EE background. Our interest is in a harness engineer, not a routing engineer., 3. Strong expertise using Zuken, building databases & making harness dwgs, 4. Excellent understanding of different automotive grade connectors, CAN network, Automotive ethernet is a bonus • Experience integration of electronics & HW components.

About the Role As a Principal ASIC Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will collaborate with PD, DFT, STA, and integration teams to ensure successful tape-outs and work closely with system teams for chip bring-up and validation. Base salary range is $180,000 - $210,000 a year. The base salary offer will depend on factors such as education, experience, training, skills, qualifications, and location. This position is also eligible for a discretionary bonus, equity and a full range of medical and other benefits. Responsibilities • Design, implement, and debug complex logic blocks., • Integrate complex IPs from internal and external vendors., • Support front-end integration activities such as Lint, CDC, synthesis, and ECO., • Participate in design and code reviews to ensure quality., • Develop functional tests/testbenches and run RTL and gate-level simulations., • Work with verification, DFT, and physical design engineers to achieve successful tape-outs., • Bring up, validate, and debug chip features; collaborate with software, firmware, and systems teams. Qualifications • BS/MS degree in Electrical Engineering or Computer Science., • 10+ years of relevant ASIC design experience., • Strong understanding of digital logic design and complex synchronous/asynchronous interfaces., • Proficiency in Verilog/SystemVerilog RTL design., • Experience in high-speed Serdes design and familiar with Ethernet (802.3) standards., • Knowledge of synthesis and static timing analysis., • Experience developing testbenches and test cases; familiarity with UVM., • Experience with gate-level simulations, chip bring-up, and validation., • Proven track record of successful production tape-outs. Preferred Qualifications • Expertise in scripting languages (Python, Tcl, Perl, Shell)., • Familiarity with DFT methodology and physical design flow., • Knowledge of UCIE, or UAlink, AXI/CHI interface is a plus., • Hands-on experience with STA and timing closure., • Strong problem-solving and planning skills., • Excellent communication and collaboration abilities. About Credo Credo’s mission is to transform connectivity at scale through fast, reliable, and energy-efficient system solutions. Our high-speed copper and optical interconnect products deliver industry-leading power and performance at up to 1.6T to meet the ever-expanding data infrastructure demands of AI. Our product portfolio includes ZeroFlap (ZF) Active Electrical Cables (AECs) and ZF optical transceivers, OmniConnect memory solutions, and a suite of retimers and DSPs for optical and copper Ethernet and PCIe, all leveraging the PILOT diagnostic and analytics software platform. Credo innovations enable our customers to connect the systems that connect the world. Credo is committed to creating an inclusive environment for all employees and welcome applicants from diverse backgrounds without regard to race, color, religion, gender, sex, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis. If you have a disability or special need that requires accommodation to navigate our website or complete the application process, email .

Job Title: PLM System Design Engineer Location: Sunnyvale Job Type: Full-Time We are seeking a highly strategic and technically strong PLM System Design Engineer to lead global PLM and supply chain transformation initiatives within a fast-paced electronics environment. The ideal candidate will have deep PLM expertise, strong business communication skills, and proven experience leading global New Product Introduction (NPI) programs. Key Responsibilities: • Lead discussions with business stakeholders to articulate the value of PLM and data foundation initiatives., • Create and deliver executive-level presentations outlining project vision, roadmap, and strategic impact., • Develop strong business cases for PLM data use cases and enterprise data foundation initiatives., • Mobilize Proof of Concepts (POCs) and scale rapid solutions across global teams., • Drive global supply chain initiatives across design, sourcing, manufacturing, logistics, fulfillment, and after-sales service., • Lead PLM strategy and execution for global New Product Introduction (NPI) programs., • Translate PLM data into actionable process improvements across enterprise and manufacturing systems., • Recommend and implement data-driven process efficiency improvements., • Oversee PLM enterprise software integrations with enterprise systems and data platforms., • Align business and technical teams across global regions., • Deliver large-scale, high-complexity global initiatives under tight timelines and ambiguity., • Bachelor’s degree in Industrial Engineering or related field (Manufacturing, Mechanical, Electrical, etc.)., • 5–7+ years of experience leading global supply chain initiatives in the electronics industry., • Deep expertise in PLM systems, enterprise integrations, and data platforms., • Extensive experience supporting global NPI initiatives., • Strong understanding of how PLM data supports enterprise, manufacturing, and supply chain processes., • Proven ability to identify high-impact data use cases and scale solutions globally., • Strong analytical, project management, and leadership skills., • Exceptional verbal, written, and executive presentation skills., • Master’s degree in Industrial Engineering or related field., • Ability to operate independently with strong ownership and conviction., • Strong problem-framing skills with a clear focus on delivering business value., • Experience driving high-quality execution across global cross-functional teams.

Below are the must haves: • Knowledge of android / Linux audio stack, • Direct experience working as QA/test engineer for audio products, • Some scripting skills (for automation) POSITION OVERVIEW Ford’s Infotainment team is looking for a skilled Audio Validation Engineer to join our Palo Alto tech hub. This role is critical in ensuring the audio quality and functional reliability of our next-generation vehicle platforms. You will focus on end-to-end testing across a sophisticated software stack where Android and Linux operate in a virtualized environment. This is a 6-month contract position with a clear path to full-time conversion for the right candidate. KEY RESPONSIBILITIES • End-to-End Audio Testing: Design and execute test strategies for the entire audio signal path, from the application layer to the physical speakers and microphones., • Android & Linux Integration: Validate audio routing, concurrency, and performance in a system where Android runs as a guest VM on a Linux host., • Multimedia & Connectivity: Test high-fidelity media playback, voice recording, and telephony (HFP), as well as seamless integration with Apple CarPlay and Android Auto., • Acoustic Quality: Validate Echo Cancellation and Noise Reduction (ECNR) performance to ensure premium voice-call quality in various driving conditions., • Safety & Vehicle Alerts: Ensure 100% reliability for safety-critical audio, including vehicle chimes, Acoustic Vehicle Alerting Systems (AVAS), and horn integration., • Advanced Debugging: Analyze system logs from both Android and Linux layers to identify and troubleshoot complex audio artifacts or routing conflicts. REQUIRED QUALIFICATIONS & SKILLS • Domain Expertise: Strong background in audio testing and validation (Automotive, Mobile, or Consumer Electronics)., • OS Frameworks: Hands-on experience with the Android Audio Stack (Audio HAL, AudioFlinger) and Linux Audio (ALSA)., • Virtualized Environments: Familiarity with testing software in multi-OS or virtualized environments (Guest/Host architectures)., • Smartphone Projection: Experience validating Apple CarPlay and Android Auto audio requirements., • Testing Tools: Proficiency with audio analysis tools (e.g., Audio Precision, Adobe Audition) and defect tracking systems (Jira). PREFERRED QUALIFICATIONS • Experience with automotive-specific audio use cases (e.g. Chimes, AVAS, V2X alerts)., • Knowledge of Bluetooth profiles (e.g. HFP, A2DP) and hands-free telephony standards., • Ability to write Python or Shell scripts for test automation and log parsing., • Degree in Electrical Engineering, Computer Science, or a related field with an emphasis on Signal Processing.

Job Description MediaTek’s Data Center team is at the forefront of innovation, driving the development of cutting-edge technologies that power the world's most advanced data centers. We are a dynamic group of system architects, packaging technology developers, and SoC design experts dedicated to creating high-performance, efficient, and reliable solutions. Our team collaborates closely to push the boundaries of technology, ensuring optimal performance, power efficiency, and scalability for data center applications. Join our Data Center team and be a part of the technological revolution that is shaping the future of data centers. If you are passionate about innovation and have the expertise to drive strategic technology development, we would love to hear from you. The Software Design Engineer role will be responsible for creating and managing a team with critical mass for data center silicon. Key responsibilities include collaborating with hardware and architect team to deliver software solutions. Develop, implement and promote methodologies and tools for software design, test and debug. Requirement • BS/MS in Electrical Engineering/Computer Engineering or or related field., • 5+ years of experience in software design & implementation., • 2+ years of experience in hands on experience in architecting software stacks for data center silicon., • Strong knowledge in Linux device driver (PCIe, Netdev, Virtio, ..), and network related software stacks (DPDK, SAI, SONiC, libfabric,…), • Proficiency in C/C++ and scripting languages (e.g., Python, Shell), • Excellent problem-solving skills and ability to work independently, • Strong communication skills and ability to collaborate in cross-functional teams Location: San Jose, California or Portland, Oregon Salary range: $190,000- $270,000. Employee may be eligible for performance bonus, short and long term incentive programs. Actual total compensation will be dependent upon the individual's skills, experience and qualifications. In addition, MediaTek provides a variety of benefits including comprehensive health insurance coverage, life and disability insurance, savings plan, Company paid holidays, Sick Leave, Vacation time, Parental leave, 401K and more. MediaTek is an Equal Opportunity Employer that is committed to inclusion and diversity to all, regardless of age, ancestry, color, disability (mental and physical), exercising the right to family care and medical leave, gender, gender expression, gender identity, genetic information, marital status, medical condition, military or veteran status, national origin, political affiliation, race, religious creed, sex (includes pregnancy, childbirth, breastfeeding and related medical conditions), and sexual orientation.

Design Engineer – Emulation & High-Speed Interfaces Palladium Solutions Development Why Join Us We’re building the next generation of full-system emulation and verification solutions—and we’re looking for a seasoned Design Engineer to help lead the way. If you’re passionate about high-speed interfaces, system-level verification, and solving complex engineering challenges at scale, this is an opportunity to make a real impact on industry-defining technology. You’ll work hands-on with Palladium and Protium emulation platforms, developing high-fidelity models and end-to-end verification environments that enable early software bring-up and accelerate silicon success. What You’ll Do • Lead the development and deployment of PHY logic and interface models for emulation platforms including Palladium and Protium, • Design, integrate, and validate high-speed interface subsystems (SerDes, chip-to-chip links) in full-system emulation environments, • Develop end-to-end verification flows, including:, • System-level modeling (microcontrollers, memories, NoC, controllers, MACs), • Custom test case development and automation, • Interface performance analysis and validation, • Convert Analog/Mixed-Signal (AMS) parallel and serial models into emulation-ready implementations with functional and bit accuracy, • Enable bare-metal driver validation and early software stack development in emulation, • Collaborate with architecture, IP, verification, and software teams to ensure smooth transitions from simulation to emulation, • Optimize multi-clock domain designs for accuracy, performance, area, and runtime, • Drive innovation in emulatable IP and AVIP solutions, influencing next-generation verification methodologies, • Support system prototyping and early bring-up for complex SoC designs What You Bring Required Qualifications • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field, • 7–15 years of experience in system-level design, verification, or emulation, • Strong experience with high-speed communication protocols, including:, • PCIe, UCIe, Ethernet, UALink, DDR, USB, SPI, JTAG, AMBA Proven expertise in: • SystemVerilog for synthesizable RTL design, • C and Python for modeling, scripting, automation, and test development, • Converting AMS designs into emulation models supporting configuration, control, and status monitoring, • Lab debug, performance analysis, and test case development, • Hands-on experience with emulation and prototyping platforms, such as:, • Palladium, Protium, Zebu, HAPS, Veloce, FPGA, • Strong understanding of verification flows, emulation acceleration, and hardware/software co-verification Nice to Have • Experience building Acceleratable Verification IP (AVIP), • Familiarity with end-to-end verification environments from simulation through emulation, • Background in system prototyping, SoC bring-up, and pre-silicon validation, • Strong analytical, debugging, and problem-solving skills, • Excellent communication, collaboration, and technical leadership abilities Make an Impact! We’re doing work that matters. Help us solve what others can’t. Join a team where your expertise directly shapes how complex systems are verified, validated, and brought to life.

Site Reliability Engineer (SRE) | San Fran Bay Area | Hybrid, 2 days in Fremont Office We’re partnering with a technology-driven organisation modernising its infrastructure and operations. They’re hiring an experienced Site Reliability Engineer to help transition from legacy systems to modern, automated, Infrastructure-as-Code environments. What You’ll Do • Build automation software in Python for cloud infrastructure, • Drive Infrastructure as Code adoption using Terraform, • Implement configuration management (Ansible/SaltStack), • Improve CI/CD pipelines, monitoring, and system reliability, • Participate in a sustainable on-call rotation What You’ll Bring • 3+ years’ experience in AWS and/or GCP production environments, • Strong Python and Linux skills, • Hands-on Terraform and IaC experience, • Experience with CI/CD and configuration management tools, • Collaborative mindset and interest in solving complex problems Why Apply • High-impact role with real ownership, • Opportunity to modernise and automate at scale, • Strong technical challenges and growth potential

Code Red is Partnered with a fast-growing startup. They are a software company in the healthtech space. Series D round of funding, located in San Francisco, New York City, + Seattle. What you’ll do: • Product Security Engineering and Software Security Engineering work, Bug Bounty, Vulnerability Management, and core ProdSec/AppSec management work., • Will be taking over a small security team and growing it., • Work with Product and Engineering teams to push out products., • Collaborate with engineering, mitigate security risks, and support shipping quickly., • Support threat modeling, shifting left, building tooling, and automating processes., • Review code designs and pull requests, SSDLC, not a generalist/SecOps role. Does this sound like you? • 8+ years' exp. working on Application or Product Security Engineering teams., • True Leadership experience, a small team is fine, but needs to have true management experience, able to influence and build a team + Engineering., • Proven track record of starting and scaling a successful Product Security program., • Excited about integrating security into product delivery without slowing things down., • Passion for security and technology, bonus points for SWE background. [leveling Engineering Manager or Sr. Engineering Manager, up to $350K base salary + equity] Cannot wait to hear more about this position? Click apply below or reach out to Erin Barry () today, and they will share more information and details about the role. Code Red Partners are extremely committed to working with equal opportunity employers helping build a diverse and inclusive workforce within Cyber Security. We put the people we work with at the heart of everything we do and dedicate all we do to playing a part in developing an industry that represents a variety of backgrounds, perspectives, and skills.

Automation CSV Engineer (Biotech/Pharma) Location – California Bay Area Please note: We are only considering W2 candidates at this time. Applications from third-party vendors or C2C arrangements will not be considered. ADVENT Engineering is an engineering and consulting firm providing expertise to the pharmaceutical and biotechnology industries. Headquartered near San Francisco, California, and with operations in the Eastern and Western US, Canada and Singapore, our company is involved in almost every facet of global pharmaceutical and biotechnology facility design and process engineering and quality system projects. ADVENT's services include process engineering, automation engineering, project engineering, facility/system design, start up and commissioning, validation and compliance consulting for distinguished and successful biotechnology and pharmaceutical manufacturing companies. The successful candidate will work with a group of engineers involved in the design, automation, commissioning and start-up of various processes, systems and facilities. A combination of strong technical aptitude, automation engineering skills and technical writing are the desired skill set. This is an outstanding opportunity to join our growing team! Position Overview We are seeking an experienced Sr. Automation CSV Engineer to support a complex automation system migration project at a large, regulated biotechnology/pharmaceutical manufacturing site in the California Bay area. The ideal candidate will bring deep, hands-on expertise in PCS and MES system migration, validation, and implementation, with a strong preference for experience in Rockwell and PharmaSuite environments. This role requires a senior-level engineer capable of independently executing and leading CSV and automation activities while collaborating closely with cross-functional teams. Key Responsibilities • Lead and execute CSV and automation activities for PCS/MES system migration projects, • Support implementation, migration, commissioning, and validation of:, • PCS systems (Rockwell, Honeywell), • MES systems (PharmaSuite, POMSnet), • SCADA and PLC platforms, • Author, review, approve, and execute CSV lifecycle documentation, including:, • Validation Plans, • Risk Assessments, • Test Protocols (IQ/OQ/PQ), • Traceability Matrices, • Validation Summary Reports, • Ensure compliance with SDLC, 21 CFR Part 11, Annex 11, Data Integrity, and GAMP 5, • Manage and document software changes throughout the SDLC per site procedures, • Support programming, configuration, commissioning, and validation of Rockwell and PharmaSuite platforms, • Collaborate with automation, IT, QA, and manufacturing teams, • Support troubleshooting, root cause analysis, and deviation investigations as needed, • Communicate effectively with stakeholders at all levels Required Qualifications • 8+ years of experience in CSV and Automation within a regulated biotech/pharma environment, • Hands-on experience with implementation, migration, and validation of:, • PCS (Rockwell and/or Honeywell), • MES (PharmaSuite, POMSnet), • SCADA/PLC systems, • Strong, hands-on expertise with Rockwell and PharmaSuite (required), • In-depth knowledge of:, • SDLC, • 21 CFR Part 11 / Annex 11, • Data Integrity, • Computerized System Validation (CSV), • Ability to work independently and collaboratively in team environments, • Excellent verbal and written communication skills Preferred Qualifications • Familiarity with S88 Batch Standard, • Experience with Rockwell software object development, • MES recipe authoring and testing experience, • Experience with Kneat Additional Information • This position requires 100% onsite support in California, • Long-term project opportunity in a regulated manufacturing environment

• Provide expert technical support for assembly and test development with a focus on advanced chiplet and multi-die packaging., • Partner with customers to clarify technical requirements, align specifications, and resolve design and integration issues., • Guide interposer design, multi-die integration, and system-level packaging considerations., • Collaborate with cross-functional teams across design, development, test, and packaging to overcome technical challenges., • Develop and deliver clear, well-structured technical documentation and presentations for both internal stakeholders and customers. Required Qualifications • Proven hands-on experience in 2.5D / 2.xD / 3D chiplet or multi-die packaging design., • Strong knowledge of interposer design and advanced packaging technologies., • Familiarity with system-level validation, test methodologies, and productization processes., • Demonstrated ability to work directly with customers and collaborate across diverse technical teams. Preferred Qualifications • Expertise in high-bandwidth interconnects, HBM integration, or multi-chip module design., • Understanding of thermal management, signal integrity (SI), and power distribution in advanced packaging., • Experience in customer-facing technical roles and/or technical program management.

Our client is seeking an experienced Package Design Engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and RF/microwave communications A/D D/A converters (ADC & DAC). You will be part of a worldwide R&D team developing high-performance package designs for ASICs for artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations. These designs include SerDes at 112G and higher, RF/Microwave ADC/DAC, DDR and more. You'll have the opportunity to collaborate with the team to create the package structures needed to enable new design, and also automate design tasks using Cadence SKILL. RESPONSIBILITIES: • Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts., • 1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest, • Package Design of critical structures for SerDes, ADC/DAC, DDR, etc., • Schedule, prioritize, & track your work across 2+ projects simultaneously, • General flip-chip BGA package design & engineering EDUCATION/EXPERIENCE & REQUIREMENTS: • BSEE or similar field and 12+ years’ experience in flip-chip-BGA package design, including high-speed SerDes, • MSEE or similar field and 10+ years’ experience in flip-chip-BGA package design, including high-speed SerDes, • Knowledge of package-level signal integrity and power integrity, to apply to package designs, • Cadence APD (allegro package designer) experience is preferred. Equivalent tool is OK., • Cooperate with our world-wide team (multiple time zones), including co-design with internal team members and external (Vendor) designers, • Self-management and organization skills