Server CPU Physical Design Engineer, Senior/Staff level - Cambridge, UK
5 days ago
Cambridge
Qualcomm Technologies International Ltd is seeking talented Physical Design Engineers to join the Nuvia CPU team in Cambridge, UK. The team develops nextâgeneration, highâperformance, powerâefficient custom CPU cores for advanced compute and serverâclass platforms. The role ranges from Senior Engineer to Staff Engineer, with responsibilities, ownership, and technical leadership scaling with experience. ⢠Own or contribute to CPU block implementation from RTL/netlist to GDS, including synthesis, floorplanning, power planning, placement, clock tree synthesis, routing, optimization, ECOs, and signâoff., ⢠Drive timing closure and physical implementation convergence across multiple modes, corners, and operating conditions., ⢠Work on highâperformance, lowâpower CPU designs with demanding performance, power, and area targets., ⢠Debug and resolve complex implementation issues related to timing, congestion, clocking, routing, IR drop, power integrity, EM, ECO closure, DRC/LVS, and physical verification., ⢠Collaborate closely with RTL, architecture, circuits, CAD, SoC, and postâsilicon teams to improve design quality, implementation efficiency, and product performance., ⢠Evaluate and contribute to the design process from concept through productization, including architecture definition, feasibility analysis, preâsilicon design and verification, and postâsilicon validation., ⢠Develop and enhance physical design flows, automation, and methodologies to improve productivity and quality of results., ⢠Use dataâdriven analysis to identify implementation bottlenecks, improve design convergence, and push PPA beyond standard targets., ⢠For Staffâlevel candidates, provide technical leadership, mentor engineers, define implementation strategies, and drive closure of critical CPU blocks or methodology initiatives., ⢠Strong experience in physical design implementation, including synthesis, floorplanning, placement, CTS, routing, timing closure, ECOs, and signâoff., ⢠Strong understanding of static timing analysis and timing closure methodologies, and tradeâoffs between timing, power, area, congestion, and routability., ⢠Knowledge of highâperformance and lowâpower implementation techniques., ⢠Handsâon experience with industryâstandard EDA tools for synthesis, place and route, STA, power analysis, physical verification, and signâoff (e.g., Genus, Innovus, Fusion Compiler, PrimeTime, Tempus, Voltus, RedHawk, Conformal)., ⢠Ability to debug complex physical design issues across timing, congestion, clocking, routing, power, and verification domains., ⢠Scripting and automation experience using TCL, Python, or Perl., ⢠Strong communication skills and the ability to work effectively in a global, crossâfunctional engineering environment., ⢠Bachelorâs degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant experience in ASIC, CPU, or physical design implementation., ⢠Masterâs degree with relevant hardware engineering experience, or a PhD with relevant CPU/ASIC/physical implementation experience., ⢠Physical design experience on CPU cores, highâperformance compute blocks, or timingâcritical ASIC designs., ⢠Experience working in advanced semiconductor process nodes, especially 7nm and below., ⢠Strong understanding of CPU PPA optimization and design convergence., ⢠Experience with lowâpower design techniques, clock optimization, useful skew, standardâcell library usage, and physicalâaware optimization., ⢠Knowledge of power integrity, IR drop, EM analysis, and power signâoff., ⢠Experience with timing ECOs and lateâstage design closure across large scenario sets., ⢠Understanding of CPU microarchitecture, logic design, or circuitâlevel implementation considerations., ⢠Experience developing physical design methodology, automation, or productivityâenhancing flows., ⢠For Staffâlevel candidates, proven ability to lead complex technical work, influence crossâfunctional teams, and mentor other engineers., ⢠Strong physical design fundamentals and enthusiasm for solving difficult implementation problems., ⢠Passion for pushing performance, power, and area to bestâinâclass levels., ⢠Ability to work independently while collaborating effectively across global teams., ⢠Structured, analytical approach to debugging, optimization, and design closure., ⢠Motivation to build highâperformance, powerâefficient server CPU products., ⢠Demonstrated ownership, technical curiosity, and a continuousâimprovement mindset., ⢠Competitive compensation package, including base salary, performanceârelated bonus, and equity opportunities., ⢠Employee Stock Purchase Plan and equity programs., ⢠Pension and retirement support, including a matching pension scheme., ⢠Health and wellbeing benefits, including medical, life, income protection, and wellbeing resources., ⢠Maternity, paternity, family, and extended leave support., ⢠Education assistance and tuition support., ⢠Relocation and immigration support where applicable., ⢠Employee assistance and resilience programs., ⢠Opportunities to connect through employee networks, community programs, volunteering, and social groups that support inclusion and collaboration., ⢠Subsidised wellbeing and lifestyle benefits, such as gym or fitness support and bicycle purchase schemes., ⢠A flexible, collaborative, and technically challenging work environment. Qualcomm is an equal opportunity employer. If you are an individual with a disability and need accommodation during the application/hiring process, please contact Qualcommâs accessibility team at disabilityâaccommodations@qualcomm.com. Qualcomm is committed to providing reasonable accommodations. For more information about this role, please contact Qualcomm Careers. #J-18808-Ljbffr